| 3 | | Radio Controller |
| 4 | | Radio Bridge |
| 5 | | Analog Bridge |
| 6 | | User IO Controller |
| 7 | | sysgen2opb |
| 8 | | WARP OPB Export Tool |
| 9 | | XBD |
| | 3 | == Interface Cores == |
| | 4 | |
| | 5 | * [wiki:RadioController Radio Controller] - Utilizes the SPI registers on the Radio Board and other pins to directly control the Radio Board. It connects through the Radio Bridge |
| | 6 | * [wiki:RadioBridge Radio Bridge] - Maps all the pins of the Radio Board to user ports |
| | 7 | * [wiki:AnalogBridge Analog Bridge] - Maps the pins of the Analog Board to user ports |
| | 8 | * [wiki:UserIOController User I/O Controller] - Provides drivers and hardware to control the LCD, Buzzer, LEDs etc. on the User I/O Board. |
| | 9 | |
| | 10 | == Board Support == |
| | 11 | |
| | 12 | * [wiki:FPGABoardXBD XBD] - Describes the WARP FPGA Board to the Xilinx tools for Base System Builder use. |
| | 13 | |
| | 14 | == System Generator Tools == |
| | 15 | |
| | 16 | ''Note: These are used only for Xilinx versions 9 and lower. As of version 10.1.02, Xilinx has added a stable EDK export flow to System Generator. The new flow creates a PLB46 slave interface with access to registers, FIFOs and shared memory blocks in the user design. This flow completely replaces sysgen2opb and the OPB Export Tool. As a result, these tools are no longer maintained.'' |
| | 17 | |
| | 18 | * [wiki:sysgen2opb sysgen2opb] - Adds the OPB interface to custom sysgen cores |
| | 19 | * [wiki:OPBExportTool WARP OPB Export Tool] - Export custom Sysgen cores to EDK |
