Changes between Version 11 and Version 12 of Exercises/13_4/SysGenExport

Timestamp:

Aug 23, 2012, 4:47:20 PM (12 years ago)

Author:

chunter

Comment:

--

Exercises/13_4/SysGenExport

@@ -34 +34 @@
 Click the small icon of the binoculars on the scope to have it choose reasonable automatic axes for the plots. This shows the output of the model: four random sequences to drive the User I/O core. Notice that the range of the top two subplots is different than the range of the bottom two due to the size of the output slices and ports (7 bits vs. 4 bits).
 
-1. 
+4. Double-click on the System Generator block in the top left of the model. This brings up a window that will allow you to export the design as a peripheral core. Verify that the compilation target is "Export as a pcore to EDK." Note: the "settings" button allows further options such as setting a core version number. This is very useful in development in order to keep track of changes that you make to your designs. For now, you can leave the default setting we provided alone.
+1. Select the part that your WARP hardware uses. For WARP v3 users, this part is the "Virtex6 xc6vlx240t-2ff156"
+1. Set the target directory of the export to be "./netlist". This will ensure that the pcore is created it a folder called "netlist" within whatever directory you placed the System Generator Model.
+1. Click "Generate."
+1. After generation has completed, navigate to the netlist folder in Windows Explorer. Within this directory is a "pcores" directory. Within this pcores directory is your peripheral core. This is exactly the same folder that was provided in the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] exercise.
+ 
 
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