Changes between Version 6 and Version 7 of Exercises/13_4/SysGenExport

Timestamp:

Aug 23, 2012, 9:25:04 AM (12 years ago)

Author:

chunter

Comment:

--

Exercises/13_4/SysGenExport

@@ -2 +2 @@
 ''(compatible with WARP v2 and WARP v3)''
 
-In the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] project, a peripheral core is provided and users connect it to the rest of the system specified in a WARP template XPS design. In this exercise, users will learn how to create this peripheral core from a tool known as Xilinx System Generator (SysGen).
+In the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] exercise, a peripheral core is provided and users connect it to the rest of the system specified in a WARP template XPS design. In this exercise, users will learn how to create this peripheral core from a tool known as Xilinx System Generator (SysGen).
 
 == Prerequisites ==
@@ -10 +10 @@
  * WARP v3: External USB JTAG cable and a micro USB cable for UART
  * Complete installation of ISE System Edition 13.4
+ * Installation of Matlab 2011a or 2011b
  * Set up a terminal on your computer using PuTTY or an alternative. Instructions to do this are available [wiki:HowTo/SetUpPuTTY instructions here].
 
@@ -15 +16 @@
 [[Image(overview.png)]]
 
-In this exercise, we provide users with a custom design with a Linear Feedback Shift Register ([http://en.wikipedia.org/wiki/Linear_feedback_shift_register LFSR]) that produces a sequence of pseudorandom values. These values are then latched by a counter circuit to slow them down and make their changes visible to the naked eye when observing a board. The output of this latch is sliced up and connected to output ports.
-
+In this exercise, we provide users with a custom design that uses a Linear Feedback Shift Register ([http://en.wikipedia.org/wiki/Linear_feedback_shift_register LFSR]) to produce a sequence of pseudorandom values. These values are then latched by a counter circuit to slow them down and make their changes visible to the naked eye when observing a board. The output of this latch is sliced up and connected to output ports. This design is provided as a Xilinx System Generator model. In this exercise, users will export this model to create the pcore that was provided in the [wiki:Exercises/13_4/IntroToXPS Introduction to XPS] exercise.
 
 
 == Instructions ==
 
-[raw-attachment:prng_useriosrc.mdl Test2]
+1. Download the [raw-attachment:prng_useriosrc.mdl System Generator Model] and open it in Matlab
+1. 
 
 = Additional Questions and Feedback =