wiki:FPGA Board

This is a legacy page which describes the first generation WARP FPGA Board - Please refer to the Hardware Platform User Guides for documentation on current WARP hardware


WARP FPGA Board v1

The main board in the platform is the FPGA board. At the heart of this design is a Xilinx Virtex-II Pro FPGA. This family of FPGAs is very well suited for the kinds of DSP-intensive operations required by wireless algorithms. For example, the FPGA provides dedicated multipliers, hardware blocks which implement efficient and fast multiplication, a critical operation in signal processing designs. The FPGAs also provide flexible and fast interconnect options for interfacing peripherals and creating multi-processor systems, two primary requirements of the platform design. The Virtex-II Pro also includes embedded PowerPC processor cores, providing an ideal resource for implementing higher layer algorithms better suited for general purpose processors than programmable logic.

While the FPGA itself provides substantial processing power, its connections to other devices and boards enable the variety of applications targeted by the platform. The FPGA board provides a 10/100 Ethernet interface for connections to standard wired networks. This connection enables real-time communication between existing wired network nodes and custom wireless network nodes implemented on WARP.

Daughtercard Slots

In addition, the FPGA board has four daughtercard slots, each wired to a large number of dedicated FPGA I/O pins. These slots house peripheral cards (three example daughtercard designs are described below). The slots are flexible enough to support a wide variety of future peripheral designs, including multimedia interfaces and specialized auxiliary processors. The four slots are functionally identical, allowing users to mount peripheral cards that best suit their application. The slot interface is documented in the repository, allowing users to design custom daughtercards.

A major challenge in designing an FPGA-based platform for computationally intensive applications is connecting multiple FPGAs together to accommodate algorithms which are too complex to fit on a single chip. A common approach is to design hardware with multiple FPGAs on a single board. Such designs have the benefit of proximity of computational resources, guaranteeing low-latency communication between processors. Two major drawbacks to this approach, however, are the added hardware design complexity and potential for wasted resources in applications which require fewer FPGAs than those mounted on a single board. We expect such applications to be common, especially in the early stages of algorithmic implementation. Thus, the FPGA board is built around a single large FPGA.

This presents the challenge of connecting multiple FPGAs together when the need arises. We address this scalability requirement by using the multi-gigabit transceivers built into the Xilinx FPGAs. Each MGT provides a full duplex 3+ Gb/sec connection between two FPGAs; multiple MGTs can be used in parallel to provide even more throughput between two boards. Eight MGTs are be routed to off-board connectors on each FPGA board, providing substantial inter-FPGA communications capabilities.

WARP FPGA Board Design Files

The FPGA board design files are available in the WARP repository.

Last modified 8 years ago Last modified on Jul 7, 2014, 8:06:30 PM