| | 1 | [[TracNav(HardwareUsersGuides/CM-PLL/TOC)]] |
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| | 3 | = CM-PLL Clock Module User Guide = |
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| | 5 | [[Image(wiki:HardwareUsersGuides/CM-PLL/files:cm_pll_sm.jpg, nolink)]] |
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| | 7 | The CM-PLL is a clock module for [wiki:HardwareUsersGuides/WARPv3 WARP v3] which generates a low-noise 80MHz clock synchronized to an off-board reference. The reference clock can be derived from the WARP v3 main oscillator, from external equipment connected to the board's MMCX jack or from another CM-PLL via the external board-to-board header. A block diagram of the CM-PLL circuits is shown below. |
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| | 9 | The CM-PLL clock module is available from [http://mangocomm.com/ Mango Communications]. |
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| | 11 | [[Image(wiki:HardwareUsersGuides/CM-PLL/files:cm_pll_block_diagram.png, nolink)]] |
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| | 13 | || [[Image(wiki:HardwareUsersGuides/WARPv3/files:important.png,nolink,valign=middle)]] || The CM-PLL board is sensitive to electrostatic discharge (ESD). You must take ESD precautions when handling the hardware. Always ensure you are grounded before touching the board. Damage due to ESD is not covered by warranty. || |
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