| 5 | | The FPGA Board has one 10/100/1000 Ethernet device present. The design uses the [http://www.marvell.com/files/products/transceivers/singleport/Alaska_SinglePort_88E1111.pdf Marvell 88e1111 Gigabit Ethernet PHY]. |
| | 5 | The FPGA Board has one 10/100/1000 Ethernet device present. The design uses the [http://www.marvell.com/files/products/transceivers/singleport/Alaska_SinglePort_88E1111.pdf Marvell 88e1111 Gigabit Ethernet PHY]. The Marvell PHY implements all the physical layer functionality and the Virtex-4 FPGA uses one of the hardened Tri-mode Ethernet MAC for the MAC layer. |
| | 6 | |
| | 7 | [[Image(HardwareUsersGuides/FPGABoard_v2.2/Files:FPGA_Board_Ethernet.jpg)]] |
| | 8 | |
| | 9 | There are six status LEDs (D1 - D6) which show the status of the physical layer link. |
| | 10 | |
| | 11 | || Tx || Green || Lights up during packet transmission || |
| | 12 | || Rx || Green || Lights up during packet reception || |
| | 13 | || Duplex || Red || Indicates the successful negotiation of a duplex link || |
| | 14 | || 10 || Red || Indicates negotiated speed of 10 Mbps || |
| | 15 | || 100 || Red || Indicates negotiated speed of 100 Mbps || |
| | 16 | || 1000 || Red || Indicates negotiated speed of 1 Gbps || |
| | 17 | |
| | 18 | |
