Changes between Version 4 and Version 5 of HardwareUsersGuides/FPGABoard_v2.2/UserIO


Ignore:
Timestamp:
Oct 8, 2009, 2:48:26 PM (15 years ago)
Author:
sgupta
Comment:

--

Legend:

Unmodified
Added
Removed
Modified

  • HardwareUsersGuides/FPGABoard_v2.2/UserIO

    v4 v5  
    1111The switches are debounced by a simple low pass filter on the board, but user applications which are sensitive to accidental or repeated rising edges should further debounce the input digitally.
    1212
    13 In our standard EDK designs, the down button is assigned to the PowerPC's soft reset input. When pushed and released, the PowerPC will reset and re-enter the user's main() function. If desired, the choice of the reset button can be changed in an EDK project's hardware specification.
     13In our standard EDK designs, the down button is assigned to the PowerPC's soft reset input. When pushed and released, the PowerPC will reset and re-enter the user's main() function. If desired, the choice of the reset button can be changed in an EDK project's hardware specification. Thus four buttons are available for user access.
    1414
    1515=== DIP Switch ===
    … …  
    1919There are 16 LEDs which can be controlled from user designs.
    2020
    21 Eight of these are connected to dedicated FPGA I/O pins- four green, four red.
     21Eight of these are connected to dedicated FPGA I/O pins- four green, four red; their layout shown in the diagram above.
    2222
    23 An additional eight LEDs, all yellow, are connected to the FPGA through an I2C I/O expander (MAX7318, component U39). User designs must use an I2C master in the FPGA to control these LEDs.
     23An additional eight LEDs (four yellow, two red and two green) are connected to the FPGA through an I2C I/O expander (MAX7318, component U39). User designs must use an I2C master in the FPGA to control these LEDs.
    2424
    2525=== Seven Segment Displays ===
    26 There are three 7-segment displays on the FPGA board. All three are connected to the FPGA through I2C I/O expanders. User designs must use an I2C master in the FPGA to control the displays.
     26There are three 7-segment displays on the FPGA board. All three are connected to the FPGA through I2C I/O expanders (U36 and U39). User designs must use an I2C master in the FPGA to control the displays.
    2727
    2828Each display includes eight LED elements- seven forming segments of a numerical digit and one acting as a small decimal point. Each element is controlled individually by separate bits in the I2C I/O expander's register bank.
    2929
    30 Your applicaiton must handle the mapping of hexadecimal digits to the 7 LED segments. Example Verilog and C code is included below which implements this mapping.
     30Your application must handle the mapping of hexadecimal digits to the 7 LED segments.
    3131
    32 '''Verilog Hex -> Seven Segment Mapping Example'''
    33 {{{
    34 #!verilog
    35 module sevenSegmentMap
    36 (
    37         input   [3:0]   fourBitInput,
    38         output  [6:0]   hexDisplay
    39 );
     32=== Custom User I/O Core ===
    4033
    41 reg     [6:0]   hexDisplay;
    42 
    43 always @(fourBitInput[3:0])
    44         case (fourBitInput[3:0])
    45                 4'b0001 : hexDisplay = ~(7'b1111001);   // 1
    46                 4'b0010 : hexDisplay = ~(7'b0100100);   // 2
    47                 4'b0011 : hexDisplay = ~(7'b0110000);   // 3
    48                 4'b0100 : hexDisplay = ~(7'b0011001);   // 4
    49                 4'b0101 : hexDisplay = ~(7'b0010010);   // 5
    50                 4'b0110 : hexDisplay = ~(7'b0000010);   // 6
    51                 4'b0111 : hexDisplay = ~(7'b1111000);   // 7
    52                 4'b1000 : hexDisplay = ~(7'b0000000);   // 8
    53                 4'b1001 : hexDisplay = ~(7'b0010000);   // 9
    54                 4'b1010 : hexDisplay = ~(7'b0001000);   // A
    55                 4'b1011 : hexDisplay = ~(7'b0000011);   // b
    56                 4'b1100 : hexDisplay = ~(7'b1000110);   // C
    57                 4'b1101 : hexDisplay = ~(7'b0100001);   // d
    58                 4'b1110 : hexDisplay = ~(7'b0000110);   // E
    59                 4'b1111 : hexDisplay = ~(7'b0001110);   // F
    60                 default : hexDisplay = ~(7'b1000000);   // 0
    61         endcase
    62 endmodule
    63 }}}
    64 
    65 '''C Hex -> Seven Segment Mapping Example'''
    66 {{{
    67 #!C
    68 unsigned char sevenSegmentMap(unsigned char x)
    69 {
    70         switch(x)
    71         {
    72                 case(0x0) : return 0x007E;
    73                 case(0x1) : return 0x0030;
    74                 case(0x2) : return 0x006D;
    75                 case(0x3) : return 0x0079;
    76                 case(0x4) : return 0x0033;
    77                 case(0x5) : return 0x005B;
    78                 case(0x6) : return 0x005F;
    79                 case(0x7) : return 0x0070;
    80                 case(0x8) : return 0x007F;
    81                 case(0x9) : return 0x007B;
    82 
    83                 case(0xA) : return 0x0077;
    84                 case(0xB) : return 0x007F;
    85                 case(0xC) : return 0x004E;
    86                 case(0xD) : return 0x007E;
    87                 case(0xE) : return 0x004F;
    88                 case(0xF) : return 0x0047;
    89                 default   : return 0x0000;
    90         }
    91 }
    92 }}}
     34We have implemented a custom core which maps all the user I/O available on the board to registers accessible to user designs. Details of the core are available [wiki:./warp_v4_userio here].
    9335
    9436=== Constraints ===