Changes between Version 1 and Version 2 of HardwareUsersGuides/RadioBoard_v1.4/Clocking


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Timestamp:
Feb 12, 2009, 10:54:46 PM (15 years ago)
Author:
murphpo
Comment:

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  • HardwareUsersGuides/RadioBoard_v1.4/Clocking

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    33== WARP Radio Board Clocking ==
     4[[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_ClockConnectors.jpg)]]
     5There are three clock domains on the Radio Board, as described below.
    46
    5 [[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_ClockConnectors.jpg)]]
     7=== RF Reference Clock ===
     8[[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_Clk_RF.png)]]
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    7 [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board]
     10The MAX2829 transceiver requires a refence clock which is multipled up by its PLL to form the RF carrier. This must be a 20MHz or 40MHz clock and must be driven into the Radio Board's MMCX jack. In standard WARP kits, the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board] drives this signal at 20MHz. If multiple Radio Boards are driven by the same RF reference clock, their RF carriers will be synchronous, though there will be a phase offset resulting from their PLLs locking at different times.
    811
    9 [http://www.analog.com/en/prod/0%2C2877%2CAD9513%2C00.html AD9513]
     12=== I/Q Sampling Clock ===
     13[[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_Clk_Sampling.png)]]
     14
     15The I/Q ADCs and DACs are driven by a common clock. This clock is produced on an on-board clock buffer (an Analog Devices [http://www.analog.com/en/prod/0%2C2877%2CAD9513%2C00.html AD9513]). The source clock for this buffer comes from an off-board source driven into a 4-pin connector. In standard WARP kits, the [wiki:HardwareUsersGuides/ClockBoard WARP Clock Board] drives this signal at 40MHz. If multiple Radio Boards are used on a single kit, they should all be driven by synchronous and in-phase sampling clocks.
     16
     17=== RSSI Sampling Clock ===
     18[[Image(HardwareUsersGuides/RadioBoard_v1.4/Images:Radio_Board_Clk_RSSI.png)]]
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     20
     21The dedicated RSSI ADC is clocked from the FPGA via the daughtercard headers. Any frequency up to 20MHz is valid. There is no requirement for this clock to be synchronous with other clocks on the Radio Board.