Changes between Initial Version and Version 1 of HardwareUsersGuides/WARPv3/EEPROM

Timestamp:

Jul 28, 2012, 7:16:28 PM (12 years ago)

Author:

murphpo

Comment:

--

HardwareUsersGuides/WARPv3/EEPROM

@@ +1 @@
+[[TracNav(HardwareUsersGuides/WARPv3/TOC)]]
+== WARP v3 User Guide: EEPROM ==
+
+The WARP v3 board includes a 128 Kbit IIC EEPROM. This device is non-volatile, retaining its data indefinitely even when power is removed. The FPGA must act as the IIC master to read and write data in the EEPROM. For details of the EEPROM IIC requirements and other specs, refer to the device datasheet (Numonyx M25P128).
+
+The write protect pin on the EEPROM is disabled. As a result the full EEPROM is readable and writable from user applications.
+
+The [wiki:/cores/w3_iic_master w3_iic_master] core is available for reading and writing the EEPROM from user code.
+
+The IIC EEPROM clock and data lines are tied to dedicated FPGA pins, listed in the UCF snippet below:
+{{{#!sh
+#I2C EEPROM
+NET "EEPROM_SCL" LOC = "AF23" | IOSTANDARD = "LVCMOS25";
+NET "EEPROM_SDA" LOC = "AG23" | IOSTANDARD = "LVCMOS25";
+}}}
+
+=== EEPROM Defaults ===
+
+During manufacturing some board-specific values are written to the top few bytes of the EEPROM. You can read these in your applications, or overwrite this data if desired.
+
+The default EEPROM values are:
+ * Tx DC offset calibration values for the RF interfaces, stored as two 2-byte values per interface
+ * Board serial number (the numeric part of W3-x-NNNNN) stored as 3-byte value
+ * Virtex-6 FPGA unique identifier (the 57-bit "device DNA"), stored as 8-byte value
+
+||= Byte Addr =||= Value =||
+|| 16364 || TxDCO_RFA_I![7:0] ||
+|| 16365 || TxDCO_RFA_I![15:8] || 
+|| 16366 || TxDCO_RFA_Q![7:0] || 
+|| 16367 || TxDCO_RFA_Q![15:8] || 
+|| 16368 || TxDCO_RFB_I![7:0] ||
+|| 16369 || TxDCO_RFB_I![15:8] || 
+|| 16370 || TxDCO_RFB_Q![7:0] || 
+|| 16371 || TxDCO_RFB_Q![15:8] || 
+|| 16372 || Board Serial Number Byte 0 (LSB) ||
+|| 16373 || Board Serial Number Byte 1 || 
+|| 16374 || Board Serial Number Byte 2 (MSB) ||
+|| 16375 || Reserved || 
+|| 16376 || FPGA DNA Byte 0 (LSB) ||
+|| 16377 || FPGA DNA Byte 1 ||
+|| 16378 || FPGA DNA Byte 2 ||
+|| 16379 || FPGA DNA Byte 3 ||
+|| 16380 || FPGA DNA Byte 4 ||
+|| 16381 || FPGA DNA Byte 5 ||
+|| 16382 || FPGA DNA Byte 6 ||
+|| 16383 || FPGA DNA Byte 7 (MSB) ||