WARP v3 User Guide: EEPROM

The WARP v3 board includes a 128 Kbit IIC EEPROM. This device is non-volatile, retaining its data indefinitely even when power is removed. The FPGA must act as the IIC master to read and write data in the EEPROM. For details of the EEPROM IIC requirements and other specs, refer to the device datasheet (Microchip 24AA128).

The write protect pin on the EEPROM is disabled. As a result the full EEPROM is readable and writable from user applications.

The w3_iic_eeprom core is available for reading and writing the EEPROM from user code.

The IIC EEPROM clock and data lines are tied to dedicated FPGA pins, listed in the UCF snippet below:


EEPROM Defaults

During manufacturing some board-specific values are written to the top few bytes of the EEPROM. The EEPROM driver provides functions for reading these values in your applications.

Please note the EEPROM does not implement any write protection. It is possible to overwrite these values from user code. We recommend you use the lowest addresses (i.e. starting at byte 0) for any application-specific EEPROM values to avoid overwriting the defaults described below.

The default EEPROM contents are:

  • Ethernet Addresses: 6-byte MAC addresses for ETH_A and ETH_B, drawn from Mango's allotment of IEEE-assigned MAC addresses (in the 40-D8-55-04-20-00 to 40-D8-55-04-2F-FF range). Please see the Ethernet page for important details on these values.
  • Tx DC offset calibration: DCO values (16-bit value per I/Q per RF interface) calibrated during manufacturing that can be applied at run-time to minimize the effects of LO leakage in transmitted signals
  • Board serial number: the numeric part of the WARP v3 board serial number (the last five digits of the W3-x-NNNNN label), stored as 24-bit value
  • FPGA ID: Virtex-6 FPGA unique identifier (the 57-bit "device DNA"), stored as 8-byte value
Byte Addr Value
16352 ETH_A_ADDR[5] (LSB)
16353 ETH_A_ADDR[4]
16354 ETH_A_ADDR[3]
16355 ETH_A_ADDR[2]
16356 ETH_A_ADDR[1]
16357 ETH_A_ADDR[0] (MSB)
16358 ETH_B_ADDR[5] (LSB)
16359 ETH_B_ADDR[4]
16360 ETH_B_ADDR[3]
16361 ETH_B_ADDR[2]
16362 ETH_B_ADDR[1]
16363 ETH_B_ADDR[0] (MSB)
16364 TxDCO_RFA_I[7:0]
16365 TxDCO_RFA_I[15:8]
16366 TxDCO_RFA_Q[7:0]
16367 TxDCO_RFA_Q[15:8]
16368 TxDCO_RFB_I[7:0]
16369 TxDCO_RFB_I[15:8]
16370 TxDCO_RFB_Q[7:0]
16371 TxDCO_RFB_Q[15:8]
16372 Board Serial Number Byte 0 (LSB)
16373 Board Serial Number Byte 1
16374 Board Serial Number Byte 2 (MSB)
16375 Reserved
16376 FPGA DNA Byte 0 (LSB)
16377 FPGA DNA Byte 1
16378 FPGA DNA Byte 2
16379 FPGA DNA Byte 3
16380 FPGA DNA Byte 4
16381 FPGA DNA Byte 5
16382 FPGA DNA Byte 6
16383 FPGA DNA Byte 7 (MSB)
Last modified 10 years ago Last modified on Sep 17, 2014, 10:30:09 AM