Changes between Version 1 and Version 2 of HardwareUsersGuides/WARPv3/EEPROM
- Timestamp:
- Aug 11, 2012, 9:09:44 PM (12 years ago)
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HardwareUsersGuides/WARPv3/EEPROM
v1 v2 6 6 The write protect pin on the EEPROM is disabled. As a result the full EEPROM is readable and writable from user applications. 7 7 8 The [wiki:/cores/w3_iic_ master w3_iic_master] core is available for reading and writing the EEPROM from user code.8 The [wiki:/cores/w3_iic_eeprom w3_iic_eeprom] core is available for reading and writing the EEPROM from user code. 9 9 10 10 The IIC EEPROM clock and data lines are tied to dedicated FPGA pins, listed in the UCF snippet below:
