| | 1 | [[TracNav(HardwareUsersGuides/WARPv3/TOC)]] |
| | 2 | = WARP v3 User Guide: Template Projects for ISE 13.4= |
| | 3 | |
| | 4 | The following template projects demonstrate how to use the various peripherals on the WARP v3 board and are good starting points for your custom designs. |
| | 5 | |
| | 6 | The projects are grouped by the version of Xilinx ISE used. We will update this page as we port the template projects to newer releases of ISE. |
| | 7 | |
| | 8 | '''Important:''' in order to use these projects you must have a local copy of the WARP peripheral cores (pcores) and associated drivers. See [wiki:edk_user_repository edk_user_repository setup] for instructions. Always update your local copy of the WARP edk_user_repository to use new template projects. |
| | 9 | |
| | 10 | === Choosing a Project === |
| | 11 | |
| | 12 | The On Board Peripherals Template Project contains the full suite of hardware components offered by a standalone WARP v3 board. The Lite version has the same basic architecture, but omits the SDRAM controller and Ethernet MACs. As a result, the Lite project will build faster. |
| | 13 | |
| | 14 | For reference, on a PC with a 3.4GHz i7-2600 processor, 16GB of RAM and running Windows 7 64-bit, build times of the template projects are: |
| | 15 | |
| | 16 | ||= Project =||= Build Time =|| |
| | 17 | || On Board Periphs || 17 minutes || |
| | 18 | || Lite || 9 minutes || |
| | 19 | |
| | 20 | Note: These times are from projects that had hardware "cleaned" such that no cached support files were used. When iterating on a design, build times will be faster as XPS re-uses cached netlists for unmodified cores. |
| | 21 | |
| | 22 | ---- |
| | 23 | |
| | 24 | == Xilinx ISE 13.4 == |
| | 25 | |
| | 26 | === On Board Peripherals Template Project === |
| | 27 | {{{ |
| | 28 | #!html |
| | 29 | <table align=right border=0 cellspacing=0 padding=0> |
| | 30 | <tr><td align=center> |
| | 31 | }}} |
| | 32 | |
| | 33 | [[Image(onboardperiph.png,width=300)]] |
| | 34 | |
| | 35 | {{{ |
| | 36 | #!html |
| | 37 | </td></tr> |
| | 38 | <tr><td align=center> |
| | 39 | }}} |
| | 40 | |
| | 41 | [attachment:onboardperiph.png Enlarge] | [raw-attachment:onboardperiph.pdf View PDF] |
| | 42 | |
| | 43 | {{{ |
| | 44 | #!html |
| | 45 | </td></tr></table> |
| | 46 | }}} |
| | 47 | |
| | 48 | This is an XPS/SDK project which implements peripheral cores to interface with every peripheral on the WARP v3 board, including: |
| | 49 | * MicroBlaze soft processor (big-endian, PLB-based design) |
| | 50 | * Block RAM for instruction/data memory |
| | 51 | * User I/O (LEDs, buttons, UART) |
| | 52 | * Dual Ethernet interfaces |
| | 53 | * MPMC for DDR3 SO-DIMM access |
| | 54 | * Peripherals for RF interface control |
| | 55 | * Timer peripheral for user code |
| | 56 | |
| | 57 | Version information: |
| | 58 | ||= Project Version =||= ISE Version =||= Arch =||= EDK Project Download =|| |
| | 59 | || 1.3 || 13.4 || MB/PLB || [http://warp.rice.edu/dl/refdes/template/w3_TemplateProject_OnBoardPeriphs_v1p3.zip w3_TemplateProject_OnBoardPeriphs_v1p3.zip] || |
| | 60 | |
| | 61 | We recommend downloading the latest version of this project that matches the version of the ISE tools you have installed. |
| | 62 | |
| | 63 | '''Release Notes:''' |
| | 64 | |
| | 65 | * v1.3 (Feb 2013): |
| | 66 | * Updated w3_clock_controller to v3.01b |
| | 67 | * New at_boot_clock_in_valid port delays at_boot config until 200MHz clock is stable |
| | 68 | * CM-MMCX switches must both be 0 (down) to select off-board sampling clock source |
| | 69 | * Removed duplicate LOC constraints from UCF |
| | 70 | * v1.2 (Jan 2013): |
| | 71 | * Updated WARP v3 pcores to latest versions (ad_controller, clock_controller, radio_controller, ad_bridge) |
| | 72 | * Added support for CM-MMCX clock module and config-time clock source selection via switch |
| | 73 | * Renamed EEPROM controller instance to w3_iic_eeprom_onBoard, to disambiguate when another instance is used for FMC EEPROM |
| | 74 | * Routed 200MHz clk to w3_clock_controller "at boot" logic, to select master clock source before MMCMs attempt lock |
| | 75 | * Added constraints for unused bi-directional I/O for radio_controller RFC/RFD SPI SDIO (XPS forces these to pins, even when unsed) |
| | 76 | * v1.1 (Nov 2012) |
| | 77 | * Swapped LSB/MSB for DIP switch, so LSB is right-most switch |
| | 78 | * Updated Ethernet constraints for ETH_A MDIO signals |
| | 79 | * Disabled MicroBlaze hardware divider by default (C_USE_DIV = 0) |
| | 80 | * v1.0 (Aug 2012) |
| | 81 | * Initial release of template project |
| | 82 | |
| | 83 | |
| | 84 | |
| | 85 | |
| | 86 | {{{ |
| | 87 | #!html |
| | 88 | <br clear=right> |
| | 89 | }}} |
| | 90 | ---- |
| | 91 | === Lite Project === |
| | 92 | |
| | 93 | {{{ |
| | 94 | #!html |
| | 95 | <table align=right border=0 cellspacing=0 padding=0> |
| | 96 | <tr><td align=center> |
| | 97 | }}} |
| | 98 | |
| | 99 | [[Image(lite.png,width=300,align=right)]] |
| | 100 | |
| | 101 | {{{ |
| | 102 | #!html |
| | 103 | </td></tr> |
| | 104 | <tr><td align=center> |
| | 105 | }}} |
| | 106 | |
| | 107 | [attachment:lite.png Enlarge] | [raw-attachment:lite.pdf View PDF] |
| | 108 | |
| | 109 | {{{ |
| | 110 | #!html |
| | 111 | </td></tr></table> |
| | 112 | }}} |
| | 113 | |
| | 114 | This is an XPS/SDK project which implements a subset of the peripheral cores from the full project above, including. |
| | 115 | * MicroBlaze soft processor (big-endian, PLB-based design) |
| | 116 | * Block RAM for instruction/data memory |
| | 117 | * User I/O (LEDs, buttons, UART) |
| | 118 | * Peripherals for RF interface control |
| | 119 | * Timer peripheral for user code |
| | 120 | |
| | 121 | If your application requires use of Ethernet or the DDR3 SO-DIMM you should use the '''On Board Peripherals''' project instead. |
| | 122 | |
| | 123 | Version information: |
| | 124 | ||= Project Version =||= ISE Version =||= Arch =||= EDK Project Download =|| |
| | 125 | || 1.3 || 13.4 || MB/PLB || [http://warp.rice.edu/dl/refdes/template/w3_TemplateProject_Lite_v1p3.zip w3_TemplateProject_Lite_v1p3.zip] || |
| | 126 | |
| | 127 | |
| | 128 | We recommend downloading the latest version of this project that matches the version of the ISE tools you have installed. |
| | 129 | |
| | 130 | * v1.3 (Feb 2013): |
| | 131 | * Updated w3_clock_controller to v3.01b |
| | 132 | * CM-MMCX switches must both be 0 (down) to select off-board sampling clock source |
| | 133 | * Removed duplicate LOC constraints from UCF |
| | 134 | * v1.2 (Jan 2013): |
| | 135 | * Updated WARP v3 pcores to latest versions (ad_controller, clock_controller, radio_controller, ad_bridge) |
| | 136 | * Added support for CM-MMCX clock module and config-time clock source selection via switch |
| | 137 | * Renamed EEPROM controller instance to w3_iic_eeprom_onBoard, to disambiguate when another instance is used for FMC EEPROM |
| | 138 | * Added top-level input for 200MHz LVDS oscillator on WARP v3 board |
| | 139 | * Routed new 200MHz clock to: |
| | 140 | * IDELAYCTRL ref clock (in TEMACs; was previously MMCM-generated 200MHz clock) |
| | 141 | * w3_clock_controller "at boot" logic, to select master clock source before MMCMs attempt lock |
| | 142 | * v1.1 (Nov 2012) |
| | 143 | * Swapped LSB/MSB for DIP switch, so LSB is right-most switch |
| | 144 | * Updated Ethernet constraints for ETH_A MDIO signals |
| | 145 | * Disabled MicroBlaze hardware divider by default (C_USE_DIV = 0) |
| | 146 | * v1.0 (Aug 2012) |
| | 147 | * Initial release of template project |
| | 148 | |
| | 149 | |
| | 150 | == Other Projects == |
| | 151 | The XPS/SDK projects for the latest [wiki:OFDMReferenceDesign OFDM Reference Design] and [wiki:WARPLab WARPLab Reference Design] are also available. Both of these reference projects are based on the '''On Board Peripherals''' template above. |
