WARP v3 User Guide: Template Projects for ISE 13.4

The following template projects demonstrate how to use the various peripherals on the WARP v3 board and are good starting points for your custom designs.

The projects are grouped by the version of Xilinx ISE used. We will update this page as we port the template projects to newer releases of ISE.

Important: in order to use these projects you must have a local copy of the WARP peripheral cores (pcores) and associated drivers. See edk_user_repository setup for instructions. Always update your local copy of the WARP edk_user_repository to use new template projects.

Choosing a Project

The On Board Peripherals Template Project contains the full suite of hardware components offered by a standalone WARP v3 board. The Lite version has the same basic architecture, but omits the SDRAM controller and Ethernet MACs. As a result, the Lite project will build faster.

For reference, on a PC with a 3.4GHz i7-2600 processor, 16GB of RAM and running Windows 7 64-bit, build times of the template projects are:

Project	Build Time
On Board Periphs	17 minutes
Lite	9 minutes

Note: These times are from projects that had hardware "cleaned" such that no cached support files were used. When iterating on a design, build times will be faster as XPS re-uses cached netlists for unmodified cores.

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Xilinx ISE 13.4

On Board Peripherals Template Project

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This is an XPS/SDK project which implements peripheral cores to interface with every peripheral on the WARP v3 board, including:

• MicroBlaze soft processor (big-endian, PLB-based design)
• Block RAM for instruction/data memory
• User I/O (LEDs, buttons, UART)
• Dual Ethernet interfaces
• MPMC for DDR3 SO-DIMM access
• Peripherals for RF interface control
• Timer peripheral for user code

Version information:

Project Version	ISE Version	Arch	EDK Project Download
1.3	13.4	MB/PLB	​w3_TemplateProject_OnBoardPeriphs_v1p3.zip

We recommend downloading the latest version of this project that matches the version of the ISE tools you have installed.

Release Notes:

• v1.3 (Feb 2013):
  • Updated w3_clock_controller to v3.01b
    • New at_boot_clock_in_valid port delays at_boot config until 200MHz clock is stable
    • CM-MMCX switches must both be 0 (down) to select off-board sampling clock source
  • Removed duplicate LOC constraints from UCF
• v1.2 (Jan 2013):
  • Updated WARP v3 pcores to latest versions (ad_controller, clock_controller, radio_controller, ad_bridge)
  • Added support for CM-MMCX clock module and config-time clock source selection via switch
  • Renamed EEPROM controller instance to w3_iic_eeprom_onBoard, to disambiguate when another instance is used for FMC EEPROM
  • Routed 200MHz clk to w3_clock_controller "at boot" logic, to select master clock source before MMCMs attempt lock
  • Added constraints for unused bi-directional I/O for radio_controller RFC/RFD SPI SDIO (XPS forces these to pins, even when unsed)
• v1.1 (Nov 2012)
  • Swapped LSB/MSB for DIP switch, so LSB is right-most switch
  • Updated Ethernet constraints for ETH_A MDIO signals
  • Disabled MicroBlaze hardware divider by default (C_USE_DIV = 0)
• v1.0 (Aug 2012)
  • Initial release of template project

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Lite Project

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This is an XPS/SDK project which implements a subset of the peripheral cores from the full project above, including.

• MicroBlaze soft processor (big-endian, PLB-based design)
• Block RAM for instruction/data memory
• User I/O (LEDs, buttons, UART)
• Peripherals for RF interface control
• Timer peripheral for user code

If your application requires use of Ethernet or the DDR3 SO-DIMM you should use the On Board Peripherals project instead.

Version information:

Project Version	ISE Version	Arch	EDK Project Download
1.3	13.4	MB/PLB	​w3_TemplateProject_Lite_v1p3.zip

We recommend downloading the latest version of this project that matches the version of the ISE tools you have installed.

• v1.3 (Feb 2013):
  • Updated w3_clock_controller to v3.01b
    • CM-MMCX switches must both be 0 (down) to select off-board sampling clock source
  • Removed duplicate LOC constraints from UCF
• v1.2 (Jan 2013):
  • Updated WARP v3 pcores to latest versions (ad_controller, clock_controller, radio_controller, ad_bridge)
  • Added support for CM-MMCX clock module and config-time clock source selection via switch
  • Renamed EEPROM controller instance to w3_iic_eeprom_onBoard, to disambiguate when another instance is used for FMC EEPROM
  • Added top-level input for 200MHz LVDS oscillator on WARP v3 board
  • Routed new 200MHz clock to:
    • IDELAYCTRL ref clock (in TEMACs; was previously MMCM-generated 200MHz clock)
    • w3_clock_controller "at boot" logic, to select master clock source before MMCMs attempt lock
• v1.1 (Nov 2012)
  • Swapped LSB/MSB for DIP switch, so LSB is right-most switch
  • Updated Ethernet constraints for ETH_A MDIO signals
  • Disabled MicroBlaze hardware divider by default (C_USE_DIV = 0)
• v1.0 (Aug 2012)
  • Initial release of template project

Other Projects

The XPS/SDK projects for the latest OFDM Reference Design and WARPLab Reference Design are also available. Both of these reference projects are based on the On Board Peripherals template above.