| 84 | | |
| 85 | | |
| 86 | | {{{ |
| 87 | | #!html |
| 88 | | <br clear=right> |
| 89 | | }}} |
| 90 | | ---- |
| 91 | | === Lite Project === |
| 92 | | |
| 93 | | {{{ |
| 94 | | #!html |
| 95 | | <table align=right border=0 cellspacing=0 padding=0> |
| 96 | | <tr><td align=center> |
| 97 | | }}} |
| 98 | | |
| 99 | | [[Image(lite.png,width=300,align=right)]] |
| 100 | | |
| 101 | | {{{ |
| 102 | | #!html |
| 103 | | </td></tr> |
| 104 | | <tr><td align=center> |
| 105 | | }}} |
| 106 | | |
| 107 | | [attachment:lite.png Enlarge] | [raw-attachment:lite.pdf View PDF] |
| 108 | | |
| 109 | | {{{ |
| 110 | | #!html |
| 111 | | </td></tr></table> |
| 112 | | }}} |
| 113 | | |
| 114 | | This is an XPS/SDK project which implements a subset of the peripheral cores from the full project above, including. |
| 115 | | * MicroBlaze soft processor (big-endian, PLB-based design) |
| 116 | | * Block RAM for instruction/data memory |
| 117 | | * User I/O (LEDs, buttons, UART) |
| 118 | | * Peripherals for RF interface control |
| 119 | | * Timer peripheral for user code |
| 120 | | |
| 121 | | If your application requires use of Ethernet or the DDR3 SO-DIMM you should use the '''On Board Peripherals''' project instead. |
| 122 | | |
| 123 | | Version information: |
| 124 | | ||= Project Version =||= ISE Version =||= Arch =||= EDK Project Download =|| |
| 125 | | || 1.3 || 13.4 || MB/PLB || [http://warp.rice.edu/dl/refdes/template/w3_TemplateProject_Lite_v1p3.zip w3_TemplateProject_Lite_v1p3.zip] || |
| 126 | | |
| 127 | | |
| 128 | | We recommend downloading the latest version of this project that matches the version of the ISE tools you have installed. |
| 129 | | |
| 130 | | * v1.3 (Feb 2013): |
| 131 | | * Updated w3_clock_controller to v3.01b |
| 132 | | * CM-MMCX switches must both be 0 (down) to select off-board sampling clock source |
| 133 | | * Removed duplicate LOC constraints from UCF |
| 134 | | * v1.2 (Jan 2013): |
| 135 | | * Updated WARP v3 pcores to latest versions (ad_controller, clock_controller, radio_controller, ad_bridge) |
| 136 | | * Added support for CM-MMCX clock module and config-time clock source selection via switch |
| 137 | | * Renamed EEPROM controller instance to w3_iic_eeprom_onBoard, to disambiguate when another instance is used for FMC EEPROM |
| 138 | | * Added top-level input for 200MHz LVDS oscillator on WARP v3 board |
| 139 | | * Routed new 200MHz clock to: |
| 140 | | * IDELAYCTRL ref clock (in TEMACs; was previously MMCM-generated 200MHz clock) |
| 141 | | * w3_clock_controller "at boot" logic, to select master clock source before MMCMs attempt lock |
| 142 | | * v1.1 (Nov 2012) |
| 143 | | * Swapped LSB/MSB for DIP switch, so LSB is right-most switch |
| 144 | | * Updated Ethernet constraints for ETH_A MDIO signals |
| 145 | | * Disabled MicroBlaze hardware divider by default (C_USE_DIV = 0) |
| 146 | | * v1.0 (Aug 2012) |
| 147 | | * Initial release of template project |
| 148 | | |
| 149 | | |
