WARP v3 User Guide: Template Projects

The following template projects demonstrate how to use the various peripherals on the WARP v3 board and are good starting points for your custom designs.

The projects are grouped by the version of Xilinx ISE used. We will update this page as we port the template projects to newer releases of ISE.

Important: in order to use these projects you must have a local copy of the WARP peripheral cores (pcores) and associated drivers. See edk_user_repository setup for instructions. Always update your local copy of the WARP edk_user_repository to use new template projects.

Xilinx ISE 14.4 and Later

On Board Peripherals Template Project

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This is an XPS/SDK project which implements peripheral cores to interface with every peripheral on the WARP v3 board, including:

  • MicroBlaze soft processor (big-endian, PLB-based design)
  • Block RAM for instruction/data memory
  • User I/O (LEDs, buttons, UART)
  • Dual Ethernet interfaces
  • MPMC for DDR3 SO-DIMM access
  • Peripherals for RF interface control
  • Timer peripheral for user code

Version information:

Project Version ISE Version Arch EDK Project Download
1.4 14.4 MB/PLB

We recommend downloading the latest version of this project that matches the version of the ISE tools you have installed.

Release Notes:

  • v1.4 (Mar 2014):
    • Updated project for XPS/SDK 14.4 and later (works through 14.7, the latest and last ISE release)
  • v1.3 (Feb 2013):
    • Updated w3_clock_controller to v3.01b
      • New at_boot_clock_in_valid port delays at_boot config until 200MHz clock is stable
      • CM-MMCX switches must both be 0 (down) to select off-board sampling clock source
    • Removed duplicate LOC constraints from UCF
  • v1.2 (Jan 2013):
    • Updated WARP v3 pcores to latest versions (ad_controller, clock_controller, radio_controller, ad_bridge)
    • Added support for CM-MMCX clock module and config-time clock source selection via switch
    • Renamed EEPROM controller instance to w3_iic_eeprom_onBoard, to disambiguate when another instance is used for FMC EEPROM
    • Routed 200MHz clk to w3_clock_controller "at boot" logic, to select master clock source before MMCMs attempt lock
    • Added constraints for unused bi-directional I/O for radio_controller RFC/RFD SPI SDIO (XPS forces these to pins, even when unsed)
  • v1.1 (Nov 2012)
    • Swapped LSB/MSB for DIP switch, so LSB is right-most switch
    • Updated Ethernet constraints for ETH_A MDIO signals
    • Disabled MicroBlaze hardware divider by default (C_USE_DIV = 0)
  • v1.0 (Aug 2012)
    • Initial release of template project

ISE 13.4

Please see TemplateProjects/13p4 for previous release of the template projects for XPS/SDK 13.4.

Other Projects

The XPS/SDK projects for the latest 802.11 Reference Design, WARPLab Reference Design, and OFDM Reference Design are also available. These are all more complex than the template project above but use the same tools and design flows.

Last modified 10 years ago Last modified on Mar 23, 2014, 2:22:20 PM

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