| 7 | | * This version uses the version 10 Xilinx tools with service pack 2 |
| 8 | | * The OPB has been deprecated. All peripherals in this design use the PLB |
| 9 | | * Fall of Tx data to rise of Tx ACK turn-around time reduced from 30 microseconds to 23 |
| | 7 | * This design requires version 10.1.02 of the Xilinx tools |
| | 8 | * Data-ACK turnaround time is now 23µs (as measured by the fall of data Tx to rise of ACK Tx) |
| | 9 | |
| | 10 | '''Hardware Changes''' |
| | 11 | * Xilinx deprecated the OPB and PLB34 busses. PLB46 is the new (and only) bus standard used in this design |
| | 12 | * The System Generator cores (OFDM transceiver, timer, packet detector & AGC) were created using Sysgen's new PLB46 export flow; sysgen2opb is no longer required |
| | 13 | * Xilinx did not port the plb_ethernet EMAC forward to PLB46. This design uses the xps_ethernetlite EMAC instead, customized to enable promiscuous mode (i.e. no receive address filtering) |
| | 14 | * The xps_centraldma pcore is used to handle DMA (since the EMAC no longer provides its own DMA) |
| | 15 | * The OFDM transceiver has a new interrupt output indicating the reception of a bad header |
| | 16 | * Fixed a few logic bugs in the transceiver's handling of multiple interrupts |
| | 17 | * Merged all user I/O into single GPIO core (LEDs, hex displays, push buttons & DIP switch); a [source:/PlatformSupport/WARPMAC/util/warp_userio.h header file] helps with the required bit masking/shifting |
| | 18 | |
| | 19 | '''Software Changes''' |
