Changes between Version 62 and Version 63 of OFDMReferenceDesign/Changelog
- Timestamp:
- Jan 8, 2010, 11:41:56 AM (14 years ago)
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OFDMReferenceDesign/Changelog
v62 v63 8 8 This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386). 9 9 10 Minor Revision: The Virtex-4 design has been updated to include the MGT Protector Core. 11 10 12 Download the full XPS project: 11 13 * Virtex-II Pro (WARP FPGA Board v1.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip OFDM_ReferenceDesign_FPGAv1_v14.0_public.zip] (88 MB) 12 * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14. 0_public.zip OFDM_ReferenceDesign_FPGAv2_v14.0_public.zip] (89MB)14 * Virtex-4 (WARP FPGA Board v2.2): [http://warp.rice.edu/bigFiles/OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip OFDM_ReferenceDesign_FPGAv2_v14.1_public.zip] (89MB) 13 15 14 16 [[BR]] … … 22 24 * Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet 23 25 * Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP). 26 * Version 14.1: Upgraded Radio Bridge and Radio Controller to version 1.22. Added MGT Protector cores for Virtex-4 MGTs. 24 27 25 28 '''Software Changes'''