wiki:OFDMReferenceDesign/Changelog

Version 63 (modified by sgupta, 14 years ago) (diff)

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WARP OFDM Reference Design Revision History

OFDM Reference Design v14.0 (2009-Nov-15)

The code and models for this design correspond to svn rev 1400.
This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).

Minor Revision: The Virtex-4 design has been updated to include the MGT Protector Core.

Download the full XPS project:


FPGA Board Version Notes
The OFDM Reference Design uses very similar hardware designs for the two versions of the WARP FPGA Board (v1 and v2). The primary difference is the use of a soft Ethernet MAC in the Virtex-II Pro FPGA and hard TEMAC in the Virtex-4. The custom WARP peripherals (OFDM transceiver, AGC, timer, radio controller, etc.) are identical in both projects.

The software projects are also very similar across boards. The same source files are used for both versions. A few #ifdef statements are used in WARPMAC to include/exclude board-specific code at compile time. The primary difference is support for user I/O. The project for the FPGA Board v1 uses an xps_gpio core as an interface to the LEDs, hex displays, buttons and switches. The FPGA Board v2 project uses the custom warp_v4_userio core and driver for the user I/O. WARPMAC provides a single API for user I/O, so MAC-level code can be fully portable between FPGA Board versions.

Hardware Changes

  • Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet
  • Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP).
  • Version 14.1: Upgraded Radio Bridge and Radio Controller to version 1.22. Added MGT Protector cores for Virtex-4 MGTs.

Software Changes

  • Updated WARPMAC to use new Ethernet hardware
  • Updated WARPMAC with new user I/O code for FPGA Board v2. One code file works for both versions, using just a few !#ifdef to compile the correct code.

Using the Design

  • The included download-csmamac.bit file implements CSMAMAC; download-nomac.bit implements NOMAC. Both are ready to download to WARP SISO or MIMO Kits.
  • The included download-csmamac.ace or download-nomac.ace can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface.
  • The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default:
    • P/p : Increase/decrease the packet detection energy threshold by 100
    • D/d : Increase/decrease the packet detection required minimum energy duration by 1
    • C/c : Increase/decrease the carrier sensing energy threshold by 100
    • F/f : Increase/decrease the 2.4GHz center frequency by 1 channel
    • S/s : Use SISO via the radio in slot 3/2
    • A : Use Alamouti 2x1 (2 transmit antennas, selection diversity between 2 receive antennas)
    • 1/2/4/6 : Use BPSK/QPSK/16-QAM/64-QAM for the full-rate modulation scheme for all transmitted payloads
    • You can add other commands to tweak your own parameters in uartRecv_callback function
  • The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.
  • The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets.

Previous Releases