Preliminary Release

Taken from :

The "simple streaming" PHY is the physical layer that students build when they take a wireless architecture class we offer here at Rice. This Fall will be the first time this class is taught on WARP, and so it's the first time that they will venture outside of the world of System Generator in order to test their designs.

We are nearly finished with the EDK project that includes the simple streaming peripheral and we will post it as an educational reference design that is analogous to the ofdm reference designs we already post. This will happen before classes start, so I'd expect it to be posted within a week or two. In the meantime, however, the underlying subsystems of the PHY each correspond to a lecture given in the course. Thus, the best documentation we have for the core right now is the course website itself:

Using the Reference Design

The design itself contains both a transmitter and a receiver. By default, the transmit mode is configured if the design is downloaded to a board with the FPGA board's dip switch set to zero (all four bits to the left). The receive mode is configured if downloaded to a board with the FPGA board's dip switch set to one (top three bits to the left and the bottom bit to the right). If you have a WARP Analog Board inserted into slot 4 of the FPGA board, the received constellation can be displayed on an oscilloscope that is capable of displaying the output of DAC1 vs. DAC2.


Preliminary Release: Simple Streaming Reference Design v00 (20MB .zip file)

Note: This is for kits with a 40MHz converter reference clock. Also, this project uses the latest Service Pack 2 v10 Xilinx tools.

Last modified 9 years ago Last modified on Jul 30, 2015, 8:40:47 AM