WARPLab 7
- Downloads
Getting Started
- Sample Buffer Sizes
- Automatic Gain Control
- Examples
- Extending WARPLab
- Debugging Errors
- Porting Code
- Benchmarks
WARPLab 7 Framework
WARPLab 7 Reference Design
Reference Design Modules
- Node
Interface Group
Baseband
Transport
Trigger Manager
Hardware
WARPLab 7.1.0 FPGA Architecture
WARPLab 7.1.0 uses the architecture established in WARPLab 7:
- Uses AXI interconnect
- IP updates to take advantage of AXI interconnect
Interconnect Architecture
Address Map
Please review the XPS project for the latest information.
Microblaze Address Map
NOTE: All Address not explicitly defined are reserved.
IP Instance | Base Address | High Address | Size |
---|---|---|---|
DLMB | 0x0000_0000 | 0x0001_FFFF | 128K |
ILMB | 0x0000_0000 | 0x0001_FFFF | 128K |
AXI GPIO | 0x4000_0000 | 0x4000_FFFF | 64K |
USB UART | 0x4060_0000 | 0x4060_FFFF | 64K |
Debug | 0x4140_0000 | 0x4140_FFFF | 64K |
AXI Timer | 0x41C0_0000 | 0x41C0_FFFF | 64K |
AXI SYSMON ADC | 0x4240_0000 | 0x4240_FFFF | 64K |
W3 I2C EEPROM On Board | 0x7040_0000 | 0x7040_FFFF | 64K |
W3 Clock Controller | 0x7042_0000 | 0x7042_FFFF | 64K |
W3 User IO | 0x7240_0000 | 0x7240_FFFF | 64K |
Ethernet FIFO (ETH B) | 0x72C0_0000 | 0x72C0_FFFF | 64K |
Ethernet FIFO (ETH A) | 0x72C2_0000 | 0x72C2_FFFF | 64K |
W3 AD Controller | 0x7600_0000 | 0x7600_FFFF | 64K |
WARPLab Trigger Proc | 0x7780_0000 | 0x7780_FFFF | 64K |
WARPLab Buffers | 0x7800_0000 | 0x787F_FFFF | 8M |
ETH A MAC | 0x7898_0000 | 0x7898_FFFF | 256K |
ETH B MAC | 0x78B0_0000 | 0x78B0_FFFF | 256K |
BRAM | 0x78CA_0000 | 0x78CA_FFFF | 64K |
WARPLab AGC | 0x78E0_0000 | 0x78E0_FFFF | 64K |
Radio Controller | 0x7AC0_0000 | 0x7AC0_FFFF | 64K |
W3 I2C EEPROM FMC | 0x7D40_0000 | 0x7D40_FFFF | 64K |
CDMA | 0x7E20_0000 | 0x7E20_FFFF | 64K |
Last modified 11 years ago
Last modified on Oct 8, 2013, 3:52:50 PM
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- WARPLab_7_1_0_interconnect_architecture.png (97.2 KB) - added by welsh 11 years ago.
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