WARPLab 7.2.0 FPGA Architecture for WARP v3 Hardware

The WARPLab 7.2.0 design for WARP v3 makes some significant changes to the underlying FPGA architecture in order to improve performance. This includes:

• Updates to AXI interconnect to use the DC bus on the Microblaze
• Increased bus width for interconnect attached to the DC bus
• Replaced AXI FIFO with AXI DMA for Ethernet A
• Addition of DDR
• Updates to Address Map

Interconnect Architecture

Address Map

Please review the XPS project for the latest information.

Microblaze Address Map

NOTE: All Address not explicitly defined are reserved.

IP Instance	Base Address	High Address	Size
DLMB	0x0000_0000	0x0001_FFFF	128K
ILMB	0x0000_0000	0x0001_FFFF	128K
Debug	0x4000_0000	0x4000_FFFF	64K
AXI GPIO	0x4010_0000	0x4010_FFFF	64K
AXI Timer	0x4080_0000	0x4080_FFFF	64K
USB UART	0x4100_0000	0x4100_FFFF	64K
AXI SYSMON ADC	0x4180_0000	0x4180_FFFF	64K
W3 I2C EEPROM On Board	0x4200_0000	0x4200_FFFF	64K
W3 I2C EEPROM FMC	0x4201_0000	0x4201_FFFF	64K
W3 Clock Controller	0x5000_0000	0x5000_FFFF	64K
W3 User IO	0x5100_0000	0x5100_FFFF	64K
WARPLab AGC	0x5180_0000	0x5180_FFFF	64K
Radio Controller	0x5200_0000	0x5200_FFFF	64K
W3 AD Controller	0x5280_0000	0x5280_FFFF	64K
WARPLab Trigger Proc	0x5300_0000	0x5300_FFFF	64K
ETH A MAC	0x7000_0000	0x7003_FFFF	256K
ETH B MAC	0x7010_0000	0x7013_FFFF	256K
AXI DMA (ETH A)	0x7020_0000	0x7020_FFFF	64K
Ethernet FIFO (ETH B)	0x7030_0000	0x7030_FFFF	64K
CDMA	0x7200_0000	0x7200_FFFF	64K
WARPLab Buffers	0x7800_0000	0x787F_FFFF	8M
BRAM	0x8000_0000	0x8001_FFFF	128K
DDR	0xC000_0000	0xFFFF_FFFF	1G