Version 5 (modified by welsh, 11 years ago) (diff) |
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WARPLab 7
- Downloads
Getting Started
- Sample Buffer Sizes
- Automatic Gain Control
- Examples
- Extending WARPLab
- Debugging Errors
- Porting Code
- Benchmarks
WARPLab 7 Framework
WARPLab 7 Reference Design
Reference Design Modules
- Node
Interface Group
Baseband
Transport
Trigger Manager
Hardware
WARPLab 7.2.0 FPGA Architecture
WARPLab 7.2.0 makes some significant changes to the underlying FPGA architecture in order to improve performance. This includes:
- Updates to AXI interconnect to use the DC bus on the Microblaze
- Increased bus width for interconnect attached to the DC bus
- Replaced AXI FIFO with AXI DMA for Ethernet A
- Addition of DDR
- Updates to Address Map
Interconnect Architecture
Address Map
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- WARPLab_7_2_0_interconnect_architecture.png (121.9 KB) - added by welsh 11 years ago.
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