WARPLab 7
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WARPLab 7 Framework
WARPLab 7 Reference Design
Reference Design Modules
- Node
Interface Group
Baseband
Transport
Trigger Manager
Hardware
WARPLab 7.3.0 FPGA Architecture for WARP v3 Hardware
The WARPLab 7.3.0 design for WARP v3 makes changes to the underlying FPGA architecture in order to improve performance for Read / Write IQ. This includes:
- Updates to the WARPLab Buffers core to move the Read / Write IQ memories out to the AXI interconnect
- Updates to the AXI Interconnect to allow DMA access to all the WARPLab Buffers
Interconnect Architecture
Address Map
Please review the XPS project for the latest information.
Microblaze Address Map
NOTE: All Address not explicitly defined are reserved.
IP Instance | Base Address | High Address | Size |
---|---|---|---|
DLMB | 0x0000_0000 | 0x0001_FFFF | 128K |
ILMB | 0x0000_0000 | 0x0001_FFFF | 128K |
Debug | 0x4000_0000 | 0x4000_FFFF | 64K |
AXI GPIO | 0x4010_0000 | 0x4010_FFFF | 64K |
AXI Timer | 0x4080_0000 | 0x4080_FFFF | 64K |
USB UART | 0x4100_0000 | 0x4100_FFFF | 64K |
AXI SYSMON ADC | 0x4180_0000 | 0x4180_FFFF | 64K |
W3 I2C EEPROM On Board | 0x4200_0000 | 0x4200_FFFF | 64K |
W3 I2C EEPROM FMC | 0x4201_0000 | 0x4201_FFFF | 64K |
W3 Clock Controller | 0x5000_0000 | 0x5000_FFFF | 64K |
W3 User IO | 0x5100_0000 | 0x5100_FFFF | 64K |
WARPLab AGC | 0x5180_0000 | 0x5180_FFFF | 64K |
Radio Controller | 0x5200_0000 | 0x5200_FFFF | 64K |
W3 AD Controller | 0x5280_0000 | 0x5280_FFFF | 64K |
WARPLab Trigger Proc | 0x5300_0000 | 0x5300_FFFF | 64K |
ETH A MAC | 0x7000_0000 | 0x7003_FFFF | 256K |
ETH B MAC | 0x7010_0000 | 0x7013_FFFF | 256K |
AXI DMA (ETH A) | 0x7020_0000 | 0x7020_FFFF | 64K |
Ethernet FIFO (ETH B) | 0x7030_0000 | 0x7030_FFFF | 64K |
CDMA | 0x7200_0000 | 0x7200_FFFF | 64K |
WARPLab Buffers | 0x7800_0000 | 0x783F_FFFF | 4M |
BRAM | 0x8000_0000 | 0x8001_FFFF | 128K |
RFA RX CTL | 0x8100_0000 | 0x8101_FFFF | 128K |
RFA TX CTL | 0x8104_0000 | 0x8105_FFFF | 128K |
RFB RX CTL | 0x8108_0000 | 0x8109_FFFF | 128K |
RFB TX CTL | 0x810C_0000 | 0x810D_FFFF | 128K |
RFC RX CTL | 0x8110_0000 | 0x8111_FFFF | 128K |
RFC TX CTL | 0x8114_0000 | 0x8115_FFFF | 128K |
RFD RX CTL | 0x8118_0000 | 0x8119_FFFF | 128K |
RFD TX CTL | 0x811C_0000 | 0x811D_FFFF | 128K |
DDR | 0xC000_0000 | 0xFFFF_FFFF | 1G |
Last modified 11 years ago
Last modified on Aug 15, 2013, 2:51:11 PM
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- WARPLab_7_3_0_interconnect_architecture.png (170.7 KB) - added by welsh 11 years ago.
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