WARPLab Reference Design Hardware Config: WARP v2

Radio Interface

  • In the 2 RF Node configuration (ie only RF A and RF B are populated), you should only use the 2RF bitstream in the download.
  • In the 4 RF Node configuration (ie all RF interfaces are populated), you should only use the 4RF bitstream in the download.

Debug Header

Updated for WARPLab 7.5.1

The debug header is configured by default to map to the following pins:

NOTE: The Debug Header is defined in the system.ucf and the connections are defined in the system.mhs

  • The Trigger output and Trigger input pins above are used with the Trigger Manager

Clock Configuration

The WARPLab reference design does not require any external clock connections. By default the reference design will use the oscillators on the WARP v2 board for all system and RF clocking.

The reference design does support both sourcing and sinking external clocks for synchronization of multiple nodes. The WARP v2 kit must be equipped with a clock board to source/sink clocks.

  • Detailed information on the WARP v2 Clocking configuration can be found here.
  • Detailed information on the WARP v2 Clock Board can be found here.

The WARPLab Reference Design assumes the Clock and Radio Boards are connected according to the specs in the Clock Connection howto.


  • Only one Ethernet connection (Eth A) on the board
    • Please note that due to hardware limitations within Xilinx peripherals, WARP v2 only supports non-jumbo Ethernet frames up to 1514 bytes.
Last modified 9 years ago Last modified on Mar 13, 2015, 11:33:05 AM

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