Changes between Version 2 and Version 3 of cores/w3_ad_bridge
- Timestamp:
- Aug 12, 2012, 3:02:14 PM (12 years ago)
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cores/w3_ad_bridge
v2 v3 16 16 || ad_RFA_TXD || Output || 12 || AD9963 TXD || RF A Tx data (DDR, I/Q interleaved) || 17 17 || ad_RFA_TXCLK || Output || 1 || AD9963 TXCLK || RF A Tx data clock || 18 || ad_RFA_TXIQ || Output || 1 || AD9963 TXIQ || RF A Tx data select ||18 || ad_RFA_TXIQ || Output || 1 || AD9963 TXIQ || RF A Tx data select (not used) || 19 19 || ad_RFB_TXD || Output || 12 || AD9963 TXD || RF B Tx data (DDR, I/Q interleaved) || 20 20 || ad_RFB_TXCLK || Output || 1 || AD9963 TXCLK || RF B Tx data clock || 21 || ad_RFB_TXIQ || Output || 1 || AD9963 TXIQ || RF B Tx data select ||21 || ad_RFB_TXIQ || Output || 1 || AD9963 TXIQ || RF B Tx data select (not used) || 22 22 23 23 24 24 '''Internal Ports:''' 25 25 ||= Port =||= Direction =||= Width =||= Description =|| 26 || user_RFA_TXD_I || Input || 12 || Tx I samples from user design ||27 || user_RFA_TXD_Q|| Input || 12 || Tx I samples from user design ||28 26 || sys_samp_clk_Tx || Input || 1 || Clock for user-supplied TXD signals || 29 27 || sys_samp_clk_Tx_90 || Input || 1 || 90 degree phase shifted version of sys_samp_clk_Tx || 28 || user_RFA_TXD_I || Input || 12 || RF A Tx I samples from user design || 29 || user_RFA_TXD_Q|| Input || 12 || RF A Tx Q samples from user design || 30 || user_RFA_TXIQ || Input || 1 || RF A Tx I/Q select (not used) || 31 || user_RFB_TXD_I || Input || 12 || RF B Tx I samples from user design || 32 || user_RFB_TXD_Q|| Input || 12 || RF B Tx Q samples from user design || 33 || user_RFB_TXIQ || Input || 1 || RF B Tx I/Q select (not used) || 30 34 31 35