Changes between Version 4 and Version 5 of cores/w3_ad_bridge

Timestamp:

Aug 12, 2012, 3:14:51 PM (12 years ago)

Author:

murphpo

Comment:

--

cores/w3_ad_bridge

@@ -27 +27 @@
 || sys_samp_clk_Tx_90 || Input || 1 || 90 degree phase shifted version of sys_samp_clk_Tx ||
 || user_RFA_TXD_I || Input || 12 || RF A Tx I samples from user design ||
-|| user_RFA_TXD_Q|| Input || 12 || RF A Tx Q samples from user design ||
+|| user_RFA_TXD_Q || Input || 12 || RF A Tx Q samples from user design ||
 || user_RFA_TXIQ || Input || 1 || RF A Tx I/Q select (ignored in DDR mode) ||
 || user_RFB_TXD_I || Input || 12 || RF B Tx I samples from user design ||
-|| user_RFB_TXD_Q|| Input || 12 || RF B Tx Q samples from user design ||
+|| user_RFB_TXD_Q || Input || 12 || RF B Tx Q samples from user design ||
 || user_RFB_TXIQ || Input || 1 || RF B Tx I/Q select (ignored in DDR mode) ||
 
-'''TXCLK''':
+=== TXCLK ===
 The AD9963 TXCLK input is used to capture the data presented on the TXD bus. In order to meet setup/hold requirements, the FPGA TXCLK output is a 90-degree phase shifted version of the clock signal for the TXD output. The TXCLK output is generated using the same IOB ODDR primitives as the TXD outputs. This design minimizes skew between the TXD and TXCLK signals.
 
 The user design must supply both sys_samp_clk_Tx and sys_samp_clk_Tx_90, assuring they are 90 degrees out of phase and synchronous to the input I/Q signals.
 
-'''TXIQ''':
+=== TXIQ ===
 The TXIQ ports are used by the AD9963 to de-interleave I/Q when the TXCLK runs at 2x the TXD data rate. The w3_ad_bridge implements a passthrough from user_RFx_TXIQ to ad_RFx_TXIQ.