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Dear all ,
I have two WARP V2 nodes and I need to share the clock between them , I found some some post in the forum regarding that but i am confused of what works for V2 and what is for V3 so could anyone help in from where to start with that ?
thanks in advance,
Regards
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Refer to the Clock Board users guide for connector labels.
To share the RF reference clock, you must connect J4 on the master node to J2 on the slave node.
To share the sampling clock, you must connect J5 on the master node to J3 on the slave node.
Be careful connecting cables to the Clock Board connectors - always apply pressure straight down to avoid damaging the MMCX pins, and avoid applying excessive force to minimize risk of damage to the Clock Board - FPGA Board connection.
After connecting clocks you must configure the slave node to use the off-board clocks. In the WARPLab and OFDM Reference Designs this is controlled by the DIP switch on the Radio Board in slot 2. Set the top two switches to 1 to select off-board clocks. Only change these switches when the node is powered off, as the switches are only read during FPGA configuration.
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Thank murphpo
Just a couple of questions to ask : what exactly is the type of MMCX cable to be used ? (RP-MMCX female jack or MMCX female jack) ? And is their any recommended supplier for the cables ?
Thanks in advance ,
Regards
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The WARP v1/v2 Clock Board has connectors with MMCX plugs. You need cables with MMCX jacks. For inter-kit connections I suggest straight (not right angle) connectors.
Cables with MMCX jacks are not widely available - we typically ordered them from RF Industries. A quicker alternative would be to combine a MMCX plug-to-plug cable (24") plus 2 MMCX jack-to-jack adapters.
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Dear murphpo,
I am facing a trouble in configuration the slave node to use the off board connection,
what i did is basically connecting J4 to J2 and J5 to J3 as you said and then switched the DIP switches labeled 3 and 4 on slot 2 to ones (as you said as well but i assumed that the top two switches are 3 and 4) is this correct ? and if it is correct what could be the problem over here ?
thanks in advance,
Last edited by Tarath (2014-Oct-16 05:19:53)
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I am facing a trouble in configuration the slave node to use the off board connection,
You need to provide details of the issue- after making the connections what did you observe?
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well basically i am trying to get the phase shift from one of the boards and one the other board, the phase keep changing ...
one of the problems was in the synchronization and i am suspecting it is still out there...
does your last replies in this post relate to WARPLAB v7.3 ? http://warpproject.org/forums/viewtopic.php?id=1833
thanks in advance,
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Yes, seems I got it wrong (again); sorry. The bottom 2 switches on the Radio Board in slot #2 control the clock source.
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Thanks a lot sir, well I have done it in the new way and once I program the slave node the sending and receiving LEDs of that node keep flushing... What could be the problem and how to solve ?
Thanks again
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Thanks a lot sir, well I have done it in the new way and once I program the slave node the sending and receiving LEDs of that node keep flushing.
Which LEDs are flashing?
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The receiving and sending LEDs on the slave nodes , the green and yallow ones on the radio board that flash when you send or recieve something
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The receiving and sending LEDs on the slave nodes , the green and yallow ones on the radio board that flash when you send or recieve something
Rapid blinking of those LEDs indicates the radio PLLs are not locked, which suggests the RF reference clock is not being received. Double check all your clock connections and switch settings. Also re-test the slave node in its default state (i.e. using its on-board clocks) to rule out local hardware problems.
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Ok one more question : I noticed some code changes in wl_example_siso_txrx_nodeSync.m which is the WARPLAB example for synchronization, this example was applied to WARP v3 and i am not sure if such changes applies for WARP v2 ... so do i need to add these changes in order for the sink node to receive off-board clocking?
the changes i am talking about are:
%Read Trigger IDs into workspace
[T_IN_ETH,T_IN_ENERGY,T_IN_AGCDONE,T_IN_REG,T_IN_D0,T_IN_D1,T_IN_D2,T_IN_D3] = wl_getTriggerInputIDs(nodes(1));
[T_OUT_BASEBAND, T_OUT_AGC, T_OUT_D0, T_OUT_D1, T_OUT_D2, T_OUT_D3] = wl_getTriggerOutputIDs(nodes(1));
%For the transmit node, we will allow Ethernet to trigger the buffer
%baseband, the AGC, and debug0 (which is mapped to pin 8 on the debug
%header)
nodes(1).wl_triggerManagerCmd('output_config_input_selection',[T_OUT_BASEBAND,T_OUT_D0],[T_IN_ETH,T_IN_REG]);
if(USE_EXTERNAL_TRIGGER)
%For the receive node, we will allow debug3 (mapped to pin 15 on the
%debug header) to trigger the buffer baseband, and the AGC
nodes(2).wl_triggerManagerCmd('output_config_input_selection',[T_OUT_BASEBAND,T_OUT_AGC],[T_IN_D3]);
else
nodes(2).wl_triggerManagerCmd('output_config_input_selection',[T_OUT_BASEBAND,T_OUT_AGC],[T_IN_ETH,T_IN_REG]);
end
%For the receive node, we enable the debounce circuity on the debug 3 input
%to deal with the fact that the signal may be noisy.
nodes(2).wl_triggerManagerCmd('input_config_debounce_mode',[T_IN_D3],'enable');
%Since the debounce circuitry is enabled, there will be a delay at the
%receiver node for its input trigger. To better align the transmitter and
%receiver, we can artifically delay the transmitters trigger outputs that
%drive the buffer baseband and the AGC.
nodes(1).wl_triggerManagerCmd('output_config_delay',[T_OUT_BASEBAND,T_OUT_AGC],[50]); %50ns delaywhich can be found in line 40-65 in http://warpproject.org/trac/browser/Res … nodeSync.m
thanks in advance,
Regards
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That m code does not affect clocking. It configures the triggering of the WARPLab buffers and AGC cores to select between the on-board trigger (typically Ethernet reception) or off-board trigger (via the debug header).
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