[845] | 1 | |
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[929] | 2 | ################################################################### |
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| 3 | # Copyright (c) 2006 Rice University |
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| 4 | # All Rights Reserved |
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| 5 | # This code is covered by the Rice-WARP license |
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| 6 | # See http://warp.rice.edu/license/ for details |
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| 7 | ################################################################### |
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| 8 | |
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| 9 | BEGIN radio_bridge |
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| 10 | |
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| 11 | ## Peripheral Options |
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| 12 | OPTION IPTYPE = PERIPHERAL |
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| 13 | OPTION IMP_NETLIST = TRUE |
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| 14 | OPTION HDL = VERILOG |
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| 15 | OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE) |
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| 16 | OPTION IP_GROUP = USER |
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| 17 | OPTION USAGE_LEVEL = BASE_USER |
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| 18 | OPTION RUN_NGCBUILD = TRUE |
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| 19 | |
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| 20 | IO_INTERFACE IO_IF = radio_bridge, IO_TYPE = WARP_RADIOBRIDGE_V1 |
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[886] | 21 | PARAMETER C_FAMILY = virtex2p, DT = STRING |
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[929] | 22 | |
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| 23 | ## Ports |
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| 24 | #################################################################################### |
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| 25 | ## User Ports |
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| 26 | ## The user must connect sources/sinks to these ports in XPS in order to use |
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| 27 | ## the radio board. The rest of the board's connections are made automatically |
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| 28 | #################################################################################### |
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| 29 | PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IS = userADCI |
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| 30 | PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IS = userADCQ |
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| 31 | |
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| 32 | PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IS = userDACI |
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| 33 | PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IS = userDACQ |
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| 34 | |
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| 35 | PORT user_RxRF_gain = "", DIR = I, VEC = [0:1], IO_IS = userRxRFG |
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| 36 | PORT user_RxBB_gain = "", DIR = I, VEC = [0:4], IO_IS = userRxBBG |
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| 37 | |
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| 38 | PORT user_Tx_gain = "", DIR = I, VEC = [0:5], IO_IS = userTxG |
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| 39 | |
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| 40 | PORT user_TxModelStart = "", DIR = O |
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| 41 | |
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| 42 | PORT user_RSSI_ADC_clk = "", DIR = I |
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| 43 | |
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| 44 | PORT user_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IS = userRSSI_D |
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| 45 | |
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| 46 | PORT user_EEPROM_IO_T = "", DIR = I |
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| 47 | PORT user_EEPROM_IO_O = "", DIR = I |
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| 48 | PORT user_EEPROM_IO_I = "", DIR = O |
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| 49 | |
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| 50 | PORT user_SHDN_external = "", DIR = I |
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| 51 | PORT user_RxEn_external = "", DIR = I |
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| 52 | PORT user_TxEn_external = "", DIR = I |
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| 53 | PORT user_RxHP_external = "", DIR = I |
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| 54 | |
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| 55 | #################################################################################### |
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| 56 | |
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| 57 | #Automatically tied to sys_clk_s, the OPB clock created by BSB |
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| 58 | # Custom clock setups may need to change this |
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| 59 | # Show defaults in System Assembly to view and change this assignment |
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[1413] | 60 | PORT converter_clock_in = "", DIR = I, SIGIS = CLK, ASSIGNMENT = REQUIRE |
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[929] | 61 | |
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| 62 | PORT converter_clock_out = "", DIR = O, SIGIS = CLK |
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| 63 | |
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| 64 | PORT radio_RSSI_ADC_clk = "", DIR = O |
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| 65 | |
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| 66 | PORT radio_DAC_I = "", DIR = O, VEC = [15:0], IO_IS = radioDACI, ENDIAN = LITTLE |
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| 67 | PORT radio_DAC_Q = "", DIR = O, VEC = [15:0], IO_IS = radioDACQ, ENDIAN = LITTLE |
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| 68 | |
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| 69 | PORT radio_ADC_I = "", DIR = I, VEC = [13:0], IO_IS = radioADCI, ENDIAN = LITTLE |
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| 70 | PORT radio_ADC_Q = "", DIR = I, VEC = [13:0], IO_IS = radioADCQ, ENDIAN = LITTLE |
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| 71 | |
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| 72 | PORT radio_B = "", DIR = O, VEC = [6:0], IO_IS = radioGain, ENDIAN = LITTLE |
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| 73 | |
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| 74 | PORT radio_ANTSW = "", DIR = O, VEC = [1:0], IO_IS = b2r_ANTSW, ENDIAN = LITTLE |
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| 75 | PORT radio_LED = "", DIR = O, VEC = [2:0], IO_IS = b2r_LED, ENDIAN = LITTLE |
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| 76 | PORT radio_DIPSW = "", DIR = I, VEC = [3:0], IO_IS = b2r_DIPSW, ENDIAN = LITTLE |
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| 77 | PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [9:0], IO_IS = b2r_RSSI_ADC_D, ENDIAN = LITTLE |
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| 78 | |
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| 79 | PORT radio_EEPROM_IO = "", DIR = IO, THREE_STATE = FALSE, IOB_STATE = BUF |
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| 80 | |
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| 81 | PORT radio_spi_clk = "", DIR = O |
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| 82 | PORT radio_spi_data = "", DIR = O |
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| 83 | PORT radio_spi_cs = "", DIR = O |
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| 84 | PORT radio_SHDN = "", DIR = O |
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| 85 | PORT radio_TxEn = "", DIR = O |
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| 86 | PORT radio_RxEn = "", DIR = O |
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| 87 | PORT radio_RxHP = "", DIR = O |
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| 88 | PORT radio_24PA = "", DIR = O |
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| 89 | PORT radio_5PA = "", DIR = O |
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| 90 | PORT radio_RX_ADC_DCS = "", DIR = O |
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| 91 | PORT radio_RX_ADC_DFS = "", DIR = O |
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| 92 | PORT radio_RX_ADC_PWDNA = "", DIR = O |
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| 93 | PORT radio_RX_ADC_PWDNB = "", DIR = O |
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| 94 | PORT radio_RSSI_ADC_CLAMP = "", DIR = O |
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| 95 | PORT radio_RSSI_ADC_HIZ = "", DIR = O |
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| 96 | PORT radio_RSSI_ADC_SLEEP = "", DIR = O |
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| 97 | PORT radio_LD = "", DIR = I |
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| 98 | PORT radio_RX_ADC_OTRA = "", DIR = I |
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| 99 | PORT radio_RX_ADC_OTRB = "", DIR = I |
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| 100 | PORT radio_RSSI_ADC_OTR = "", DIR = I |
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| 101 | PORT radio_DAC_PLL_LOCK = "", DIR = I |
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| 102 | PORT radio_DAC_RESET = "", DIR = O |
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| 103 | |
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[1056] | 104 | PORT controller_logic_clk = "", DIR = I |
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[929] | 105 | PORT controller_spi_clk = "", DIR = I |
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| 106 | PORT controller_spi_data = "", DIR = I |
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| 107 | PORT controller_radio_cs = "", DIR = I |
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| 108 | PORT controller_dac_cs = "", DIR = I |
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| 109 | PORT controller_SHDN = "", DIR = I |
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| 110 | PORT controller_TxEn = "", DIR = I |
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| 111 | PORT controller_RxEn = "", DIR = I |
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| 112 | PORT controller_RxHP = "", DIR = I |
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| 113 | PORT controller_24PA = "", DIR = I |
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| 114 | PORT controller_5PA = "", DIR = I |
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| 115 | PORT controller_ANTSW = "", DIR = I, VEC = [0:1], IO_IS = c2b_ANTSW |
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| 116 | PORT controller_LED = "", DIR = I, VEC = [0:2], IO_IS = c2b_LED |
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| 117 | PORT controller_RX_ADC_DCS = "", DIR = I |
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| 118 | PORT controller_RX_ADC_DFS = "", DIR = I |
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| 119 | PORT controller_RX_ADC_PWDNA = "", DIR = I |
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| 120 | PORT controller_RX_ADC_PWDNB = "", DIR = I |
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| 121 | PORT controller_RSSI_ADC_CLAMP = "", DIR = I |
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| 122 | PORT controller_RSSI_ADC_HIZ = "", DIR = I |
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| 123 | PORT controller_RSSI_ADC_SLEEP = "", DIR = I |
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| 124 | PORT controller_DIPSW = "", DIR = O, VEC = [0:3], IO_IS = c2b_DIPSW |
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| 125 | PORT controller_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IS = c2b_RSSI_ADC_D |
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| 126 | PORT controller_LD = "", DIR = O |
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| 127 | PORT controller_RX_ADC_OTRA = "", DIR = O |
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| 128 | PORT controller_RX_ADC_OTRB = "", DIR = O |
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| 129 | PORT controller_RSSI_ADC_OTR = "", DIR = O |
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| 130 | PORT controller_DAC_PLL_LOCK = "", DIR = O |
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| 131 | PORT controller_DAC_RESET = "", DIR = I |
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| 132 | PORT controller_TxStart = "", DIR = I |
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| 133 | PORT dac_spi_data = "", DIR = O |
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| 134 | PORT dac_spi_cs = "", DIR = O |
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| 135 | PORT dac_spi_clk = "", DIR = O |
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| 136 | PORT controller_SHDN_external = "", DIR = O |
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| 137 | PORT controller_RxEn_external = "", DIR = O |
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| 138 | PORT controller_TxEn_external = "", DIR = O |
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| 139 | PORT controller_RxHP_external = "", DIR = O |
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| 140 | |
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| 141 | END |
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