1 | |
---|
2 | ################################################################### |
---|
3 | # Copyright (c) 2013 Mango Communications |
---|
4 | # All Rights Reserved |
---|
5 | # This code is covered by the WARP open-source license |
---|
6 | # See http://warpproject.org/license/ for details |
---|
7 | ################################################################### |
---|
8 | |
---|
9 | BEGIN radio_bridge |
---|
10 | |
---|
11 | ## Peripheral Options |
---|
12 | OPTION IPTYPE = PERIPHERAL |
---|
13 | OPTION IMP_NETLIST = TRUE |
---|
14 | OPTION HDL = VERILOG |
---|
15 | OPTION ARCH_SUPPORT_MAP = (virtex4=DEVELOPMENT) |
---|
16 | OPTION USAGE_LEVEL = BASE_USER |
---|
17 | OPTION DESC = WARP Radio Board Bridge Core |
---|
18 | OPTION LONG_DESC = "Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards." |
---|
19 | OPTION IP_GROUP = USER |
---|
20 | OPTION RUN_NGCBUILD = FALSE |
---|
21 | OPTION STYLE = HDL |
---|
22 | |
---|
23 | IO_INTERFACE IO_IF = HW_Ports, IO_TYPE = W2_RADIOBRIDGE_V0 |
---|
24 | IO_INTERFACE IO_IF = USER_Ports, IO_TYPE = W2_RADIOBRIDGE_V0 |
---|
25 | |
---|
26 | PARAMETER C_FAMILY = virtex4, DT = STRING |
---|
27 | |
---|
28 | #This clock must match the sampling clock at the Radio Board (the one driven by the Clock Board via the twisted pair cable) |
---|
29 | PORT samp_clock = "", DIR = I, SIGIS = CLK, CLK_FREQ = 40000000, IO_IF = USER_Ports, ASSIGNMENT = REQUIRE, IO_IS = user_sampClock |
---|
30 | |
---|
31 | ## User Ports |
---|
32 | PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IF = USER_Ports, IO_IS = userADCI |
---|
33 | PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IF = USER_Ports, IO_IS = userADCQ |
---|
34 | |
---|
35 | PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IF = USER_Ports, IO_IS = userDACI |
---|
36 | PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IF = USER_Ports, IO_IS = userDACQ |
---|
37 | |
---|
38 | PORT user_ADC_I_OTR = "", DIR = O, IO_IF = USER_Ports, IO_IS = ADC_I_OTR |
---|
39 | PORT user_ADC_Q_OTR = "", DIR = O, IO_IF = USER_Ports, IO_IS = ADC_Q_OTR |
---|
40 | |
---|
41 | PORT user_RSSI_ADC_D = "", DIR = O, VEC = [9:0], IO_IF = USER_Ports, IO_IS = user_RSSI_ADC_D |
---|
42 | PORT user_RSSI_ADC_CLK = "", DIR = I, IO_IF = USER_Ports, IO_IS = user_RSSI_ADC_CLK |
---|
43 | |
---|
44 | ## Radio Bridge <-> Radio Board ports |
---|
45 | PORT radio_DAC_I = "", DIR = O, VEC = [15:0], IO_IS = radioDACI, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioDACI |
---|
46 | PORT radio_DAC_Q = "", DIR = O, VEC = [15:0], IO_IS = radioDACQ, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioDACQ |
---|
47 | |
---|
48 | PORT radio_ADC_I = "", DIR = I, VEC = [13:0], IO_IS = radioADCI, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioADCI |
---|
49 | PORT radio_ADC_Q = "", DIR = I, VEC = [13:0], IO_IS = radioADCQ, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioADCQ |
---|
50 | |
---|
51 | PORT radio_ADC_I_OTR = "", DIR = I, IO_IF = HW_Ports, IO_IS = radio_ADC_I_OTR |
---|
52 | PORT radio_ADC_Q_OTR = "", DIR = I, IO_IF = HW_Ports, IO_IS = radio_ADC_Q_OTR |
---|
53 | |
---|
54 | PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [9:0], IO_IF = HW_Ports, IO_IS = radio_RSSI_ADC_D |
---|
55 | PORT radio_RSSI_ADC_CLK = "", DIR = O, IO_IF = HW_Ports, IO_IS = radio_RSSI_ADC_CLK |
---|
56 | END |
---|