[845] | 1 | |
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[929] | 2 | ################################################################### |
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[2031] | 3 | # Copyright (c) 2013 Mango Communications |
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[929] | 4 | # All Rights Reserved |
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[2031] | 5 | # This code is covered by the WARP open-source license |
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| 6 | # See http://warpproject.org/license/ for details |
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[929] | 7 | ################################################################### |
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| 8 | |
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| 9 | BEGIN radio_bridge |
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| 10 | |
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| 11 | ## Peripheral Options |
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| 12 | OPTION IPTYPE = PERIPHERAL |
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| 13 | OPTION IMP_NETLIST = TRUE |
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| 14 | OPTION HDL = VERILOG |
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[1881] | 15 | OPTION ARCH_SUPPORT_MAP = (virtex4=DEVELOPMENT) |
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[1700] | 16 | OPTION USAGE_LEVEL = BASE_USER |
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| 17 | OPTION DESC = WARP Radio Board Bridge Core |
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| 18 | OPTION LONG_DESC = "Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards." |
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[929] | 19 | OPTION IP_GROUP = USER |
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[1700] | 20 | OPTION RUN_NGCBUILD = FALSE |
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| 21 | OPTION STYLE = HDL |
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[929] | 22 | |
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[1881] | 23 | IO_INTERFACE IO_IF = HW_Ports, IO_TYPE = W2_RADIOBRIDGE_V0 |
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| 24 | IO_INTERFACE IO_IF = USER_Ports, IO_TYPE = W2_RADIOBRIDGE_V0 |
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[1700] | 25 | |
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[1881] | 26 | PARAMETER C_FAMILY = virtex4, DT = STRING |
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[1700] | 27 | |
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[1881] | 28 | #This clock must match the sampling clock at the Radio Board (the one driven by the Clock Board via the twisted pair cable) |
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| 29 | PORT samp_clock = "", DIR = I, SIGIS = CLK, CLK_FREQ = 40000000, IO_IF = USER_Ports, ASSIGNMENT = REQUIRE, IO_IS = user_sampClock |
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[929] | 30 | |
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| 31 | ## User Ports |
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[1881] | 32 | PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IF = USER_Ports, IO_IS = userADCI |
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| 33 | PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IF = USER_Ports, IO_IS = userADCQ |
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[929] | 34 | |
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[1881] | 35 | PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IF = USER_Ports, IO_IS = userDACI |
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| 36 | PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IF = USER_Ports, IO_IS = userDACQ |
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[929] | 37 | |
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[1881] | 38 | PORT user_ADC_I_OTR = "", DIR = O, IO_IF = USER_Ports, IO_IS = ADC_I_OTR |
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| 39 | PORT user_ADC_Q_OTR = "", DIR = O, IO_IF = USER_Ports, IO_IS = ADC_Q_OTR |
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[2031] | 40 | |
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| 41 | PORT user_RSSI_ADC_D = "", DIR = O, VEC = [9:0], IO_IF = USER_Ports, IO_IS = user_RSSI_ADC_D |
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| 42 | PORT user_RSSI_ADC_CLK = "", DIR = I, IO_IF = USER_Ports, IO_IS = user_RSSI_ADC_CLK |
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[1705] | 43 | |
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[1881] | 44 | ## Radio Bridge <-> Radio Board ports |
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| 45 | PORT radio_DAC_I = "", DIR = O, VEC = [15:0], IO_IS = radioDACI, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioDACI |
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| 46 | PORT radio_DAC_Q = "", DIR = O, VEC = [15:0], IO_IS = radioDACQ, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioDACQ |
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[929] | 47 | |
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[1881] | 48 | PORT radio_ADC_I = "", DIR = I, VEC = [13:0], IO_IS = radioADCI, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioADCI |
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| 49 | PORT radio_ADC_Q = "", DIR = I, VEC = [13:0], IO_IS = radioADCQ, ENDIAN = LITTLE, IO_IF = HW_Ports, IO_IS = radioADCQ |
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[929] | 50 | |
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[1881] | 51 | PORT radio_ADC_I_OTR = "", DIR = I, IO_IF = HW_Ports, IO_IS = radio_ADC_I_OTR |
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| 52 | PORT radio_ADC_Q_OTR = "", DIR = I, IO_IF = HW_Ports, IO_IS = radio_ADC_Q_OTR |
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[929] | 53 | |
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[2031] | 54 | PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [9:0], IO_IF = HW_Ports, IO_IS = radio_RSSI_ADC_D |
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| 55 | PORT radio_RSSI_ADC_CLK = "", DIR = O, IO_IF = HW_Ports, IO_IS = radio_RSSI_ADC_CLK |
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[929] | 56 | END |
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