1 | #ifndef WARP_CLOCK_CONTROLLER_H |
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2 | #define WARP_CLOCK_CONTROLLER_H |
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3 | |
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4 | #include "xbasic_types.h" |
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5 | #include "xstatus.h" |
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6 | #include "xil_io.h" |
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7 | |
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8 | #define WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET (0x00000000) |
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9 | #define WARP_CLOCK_CONTROLLER_SLV_REG0_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000000) |
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10 | #define WARP_CLOCK_CONTROLLER_SLV_REG1_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000004) |
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11 | #define WARP_CLOCK_CONTROLLER_SLV_REG2_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000008) |
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12 | #define WARP_CLOCK_CONTROLLER_SLV_REG3_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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13 | #define WARP_CLOCK_CONTROLLER_SLV_REG4_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000010) |
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14 | #define WARP_CLOCK_CONTROLLER_SLV_REG5_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000014) |
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15 | #define WARP_CLOCK_CONTROLLER_SLV_REG6_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x00000018) |
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16 | #define WARP_CLOCK_CONTROLLER_SLV_REG7_OFFSET (WARP_CLOCK_CONTROLLER_USER_SLV_SPACE_OFFSET + 0x0000001C) |
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17 | |
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18 | /* Address map: |
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19 | HDL is coded [MSB:LSB] = [0:31] |
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20 | regX[0] maps to 0x80000000 in C driver |
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21 | regX[31] maps to 0x00000001 in C driver |
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22 | |
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23 | 0: Config: {clk_div_sel[2:0], 1'b0, samp_func, rfref_func, 26'b0} |
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24 | [29:31] Clock divider bit sel (00=0.5*busclk, 01=0.25*busclk, ...) 0x00000003 |
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25 | [28 ] Reserved |
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26 | [ 27] samp buf reset (active low) 0x00000010 |
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27 | [ 26] rf ref buf reset (active low) 0x00000020 |
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28 | [0 :25] Reserved |
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29 | |
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30 | 1: SPI Tx |
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31 | [24:31] Tx data byte |
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32 | [17:23] 7-bit register address (0x00 to 0xFF all valid) |
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33 | [11:16] 6'b0 (always zero) |
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34 | [ 9:10] Num bytes to Tx/Rx; must be 2'b0 for 1-byte Tx/Rx |
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35 | [ 8] RW# 1=Read, 0=Write |
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36 | [ 7] samp buf chip select mask |
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37 | [ 6] rf ref buf chip select mask |
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38 | [ 0: 5] Reserved |
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39 | |
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40 | 2: SPI Rx: {samp_rxByte, rfref_rxByte, 16'b0} |
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41 | [24:31] SPI Rx byte for samp buf 0x00FF |
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42 | [16:23] SPI Rx byte for rf ref buf 0xFF00 |
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43 | [ 0:15] Reserved 0xFFFF0000 |
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44 | |
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45 | 3: RW: User reset outputs |
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46 | [31] usr_reset0 |
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47 | [30] usr_reset1 |
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48 | [29] usr_reset2 |
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49 | [28] usr_reset3 |
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50 | [0:27] reserved |
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51 | |
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52 | 4: RO: User status inputs |
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53 | [0:31] usr_status input |
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54 | |
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55 | 5-15: Reserved |
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56 | */ |
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57 | #define CLKCTRL_REG_CONFIG WARP_CLOCK_CONTROLLER_SLV_REG0_OFFSET |
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58 | #define CLKCTRL_REG_SPITX WARP_CLOCK_CONTROLLER_SLV_REG1_OFFSET |
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59 | #define CLKCTRL_REG_SPIRX WARP_CLOCK_CONTROLLER_SLV_REG2_OFFSET |
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60 | |
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61 | #define CLKCTRL_REG_CONFIG_MASK_CLKDIV 0x03 |
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62 | #define CLKCTRL_REG_CONFIG_MASK_SAMP_FUNC 0x10 |
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63 | #define CLKCTRL_REG_CONFIG_MASK_RFREF_FUNC 0x20 |
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64 | |
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65 | #define CLKCTRL_REG_SPITX_SAMP_CS 0x01000000 |
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66 | #define CLKCTRL_REG_SPITX_RFREF_CS 0x02000000 |
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67 | #define CLKCTRL_REG_SPITX_RNW 0x00800000 |
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68 | |
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69 | #define CLK_SAMP_CS CLKCTRL_REG_SPITX_SAMP_CS |
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70 | #define CLK_RFREF_CS CLKCTRL_REG_SPITX_RFREF_CS |
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71 | |
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72 | #define CLK_SAMP_OUTSEL_FMC 0x01 |
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73 | #define CLK_SAMP_OUTSEL_CLKMODHDR 0x02 |
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74 | #define CLK_SAMP_OUTSEL_FPGA 0x04 |
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75 | #define CLK_SAMP_OUTSEL_AD_RFA 0x08 |
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76 | #define CLK_SAMP_OUTSEL_AD_RFB 0x10 |
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77 | |
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78 | #define CLK_RFREF_OUTSEL_FMC 0x20 |
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79 | #define CLK_RFREF_OUTSEL_CLKMODHDR 0x40 |
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80 | #define CLK_RFREF_OUTSEL_RFAB 0x80 |
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81 | |
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82 | #define CLK_OUTPUT_ON 1 |
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83 | #define CLK_OUTPUT_OFF 2 |
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84 | |
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85 | #define CLK_INSEL_ONBOARD 1 |
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86 | #define CLK_INSEL_CLKMOD 2 |
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87 | |
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88 | u32 clk_spi_read(u32 baseaddr, u32 csMask, u8 regAddr); |
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89 | void clk_spi_write(u32 baseaddr, u32 csMask, u8 regAddr, u8 txByte); |
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90 | int clk_init(u32 baseaddr, u8 clkDiv); |
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91 | int clk_config_outputs(u32 baseaddr, u8 clkOutMode, u32 clkOutSel); |
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92 | int clk_config_dividers(u32 baseaddr, u8 clkDiv, u32 clkOutSel); |
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93 | int clk_config_input_rf_ref(u32 baseaddr, u8 clkInSel); |
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94 | |
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95 | #endif /** WARP_CLOCK_CONTROLLER_H */ |
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