1 | /***************************************************************************** |
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2 | * Filename: /home/sgupta/edkwork/hex_disp_ise/custom_periph/MyProcessorIPLib/drivers/warp_v4_userio_v1_00_a/src/warp_v4_userio.h |
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3 | * Version: 1.00.a |
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4 | * Description: warp_v4_userio Driver Header File |
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5 | * Date: Mon Oct 5 10:19:41 2009 (by Create and Import Peripheral Wizard) |
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6 | *****************************************************************************/ |
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7 | |
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8 | #ifndef WARP_V4_USERIO_H |
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9 | #define WARP_V4_USERIO_H |
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10 | |
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11 | /***************************** Include Files *******************************/ |
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12 | |
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13 | #include "xbasic_types.h" |
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14 | #include "xstatus.h" |
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15 | #include "xio.h" |
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16 | |
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17 | /************************** Constant Definitions ***************************/ |
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18 | |
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19 | |
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20 | /** |
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21 | * User Logic Slave Space Offsets |
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22 | * -- SLV_REG0 : user logic slave module register 0 |
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23 | * -- SLV_REG1 : user logic slave module register 1 |
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24 | * -- SLV_REG2 : user logic slave module register 2 |
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25 | * -- SLV_REG3 : user logic slave module register 3 |
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26 | * -- SLV_REG4 : user logic slave module register 4 |
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27 | */ |
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28 | #define WARP_V4_USERIO_USER_SLV_SPACE_OFFSET (0x00000000) |
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29 | #define WARP_V4_USERIO_SLV_REG0_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000000) |
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30 | #define WARP_V4_USERIO_SLV_REG1_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000004) |
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31 | #define WARP_V4_USERIO_SLV_REG2_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000008) |
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32 | #define WARP_V4_USERIO_SLV_REG3_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x0000000C) |
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33 | #define WARP_V4_USERIO_SLV_REG4_OFFSET (WARP_V4_USERIO_USER_SLV_SPACE_OFFSET + 0x00000010) |
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34 | |
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35 | |
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36 | /**************************** Type Definitions *****************************/ |
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37 | |
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38 | |
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39 | /***************** Macros (Inline Functions) Definitions *******************/ |
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40 | |
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41 | /** |
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42 | * |
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43 | * Write a value to a WARP_V4_USERIO register. A 32 bit write is performed. |
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44 | * If the component is implemented in a smaller width, only the least |
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45 | * significant data is written. |
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46 | * |
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47 | * @param BaseAddress is the base address of the WARP_V4_USERIO device. |
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48 | * @param RegOffset is the register offset from the base to write to. |
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49 | * @param Data is the data written to the register. |
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50 | * |
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51 | * @return None. |
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52 | * |
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53 | * @note |
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54 | * C-style signature: |
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55 | * void WARP_V4_USERIO_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data) |
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56 | * |
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57 | */ |
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58 | #define WARP_V4_USERIO_mWriteReg(BaseAddress, RegOffset, Data) \ |
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59 | XIo_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data)) |
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60 | |
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61 | /** |
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62 | * |
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63 | * Read a value from a WARP_V4_USERIO register. A 32 bit read is performed. |
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64 | * If the component is implemented in a smaller width, only the least |
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65 | * significant data is read from the register. The most significant data |
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66 | * will be read as 0. |
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67 | * |
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68 | * @param BaseAddress is the base address of the WARP_V4_USERIO device. |
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69 | * @param RegOffset is the register offset from the base to write to. |
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70 | * |
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71 | * @return Data is the data from the register. |
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72 | * |
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73 | * @note |
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74 | * C-style signature: |
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75 | * Xuint32 WARP_V4_USERIO_mReadReg(Xuint32 BaseAddress, unsigned RegOffset) |
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76 | * |
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77 | */ |
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78 | #define WARP_V4_USERIO_mReadReg(BaseAddress, RegOffset) \ |
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79 | XIo_In32((BaseAddress) + (RegOffset)) |
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80 | |
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81 | |
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82 | /** |
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83 | * |
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84 | * Write/Read 32 bit value to/from WARP_V4_USERIO user logic slave registers. |
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85 | * |
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86 | * @param BaseAddress is the base address of the WARP_V4_USERIO device. |
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87 | * @param RegOffset is the offset from the slave register to write to or read from. |
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88 | * @param Value is the data written to the register. |
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89 | * |
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90 | * @return Data is the data from the user logic slave register. |
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91 | * |
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92 | * @note |
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93 | * C-style signature: |
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94 | * void WARP_V4_USERIO_mWriteSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Value) |
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95 | * Xuint32 WARP_V4_USERIO_mReadSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset) |
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96 | * |
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97 | */ |
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98 | #define WARP_V4_USERIO_mWriteSlaveReg0(BaseAddress, RegOffset, Value) \ |
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99 | XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG0_OFFSET) + (RegOffset), (Xuint32)(Value)) |
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100 | #define WARP_V4_USERIO_mWriteSlaveReg1(BaseAddress, RegOffset, Value) \ |
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101 | XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG1_OFFSET) + (RegOffset), (Xuint32)(Value)) |
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102 | #define WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, RegOffset, Value) \ |
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103 | XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG2_OFFSET) + (RegOffset), (Xuint32)(Value)) |
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104 | #define WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, RegOffset, Value) \ |
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105 | XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG3_OFFSET) + (RegOffset), (Xuint32)(Value)) |
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106 | #define WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, RegOffset, Value) \ |
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107 | XIo_Out32((BaseAddress) + (WARP_V4_USERIO_SLV_REG4_OFFSET) + (RegOffset), (Xuint32)(Value)) |
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108 | |
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109 | #define WARP_V4_USERIO_mReadSlaveReg0(BaseAddress, RegOffset) \ |
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110 | XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG0_OFFSET) + (RegOffset)) |
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111 | #define WARP_V4_USERIO_mReadSlaveReg1(BaseAddress, RegOffset) \ |
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112 | XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG1_OFFSET) + (RegOffset)) |
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113 | #define WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, RegOffset) \ |
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114 | XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG2_OFFSET) + (RegOffset)) |
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115 | #define WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, RegOffset) \ |
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116 | XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG3_OFFSET) + (RegOffset)) |
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117 | #define WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, RegOffset) \ |
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118 | XIo_In32((BaseAddress) + (WARP_V4_USERIO_SLV_REG4_OFFSET) + (RegOffset)) |
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119 | |
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120 | |
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121 | /* Register descriptions |
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122 | * SlaveReg0 - Output register: 8 LSB bits output to the LEDs |
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123 | * SlaveReg1 - Input register: 4 LSB are pushbuttons and 4 above that are dip switches |
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124 | * SlaveReg2 - Hex displays in number mode. When in number mode |
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125 | the bits in this register are mapped to numbers on the displays |
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126 | * SlaveReg3 - Hex displays in raw mode. When in raw mode, the bits are directly |
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127 | output to the hex displays |
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128 | * SlaveReg4 - Control register: Setup parameters for hex display control |
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129 | |
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130 | Refer to http://warp.rice.edu/trac/wiki/HardwareUsersGuides/FPGABoard_v2.2/UserIO for details. |
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131 | */ |
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132 | |
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133 | #define LEFTHEX_OFFSET_NUM 16 |
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134 | #define MIDHEX_OFFSET_NUM 8 |
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135 | #define RIGHTHEX_OFFSET_NUM 0 |
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136 | |
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137 | #define LEFTHEX_OFFSET_RAW 24 |
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138 | #define MIDHEX_OFFSET_RAW 16 |
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139 | #define RIGHTHEX_OFFSET_RAW 8 |
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140 | #define IOEX_LEDS_OFFSET_RAW 0 |
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141 | |
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142 | #define LEDMASK 0x000000FF |
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143 | #define PBMASK 0x0000000F |
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144 | #define DIPMASK 0x000000F0 |
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145 | |
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146 | //Bit masks for user inputs (buttons & switches) |
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147 | #define USERIO_MASK_DIPSW 0xF0 |
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148 | #define USERIO_MASK_PB 0x0F |
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149 | #define USERIO_MASK_PBC 0x01 |
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150 | #define USERIO_MASK_PBR 0x02 |
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151 | #define USERIO_MASK_PBL 0x04 |
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152 | #define USERIO_MASK_PBU 0x08 |
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153 | |
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154 | |
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155 | #define LED_OFFSET 0 |
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156 | #define PB_OFFSET 0 |
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157 | #define DIP_OFFSET 4 |
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158 | |
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159 | #define LEFTHEX_NUM_MODE 0x00000004 |
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160 | #define MIDHEX_NUM_MODE 0x00000002 |
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161 | #define RIGHTHEX_NUM_MODE 0x00000001 |
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162 | |
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163 | #define LEFTHEX_NUM_VAL 0x001F0000 |
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164 | #define MIDHEX_NUM_VAL 0x00001F00 |
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165 | #define RIGHTHEX_NUM_VAL 0x0000001F |
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166 | |
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167 | #define HEX_OFF_ON 0x00000020 |
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168 | |
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169 | |
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170 | #define WarpV4_UserIO_Leds(BaseAddress, Value) \ |
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171 | WARP_V4_USERIO_mWriteSlaveReg0(BaseAddress, 0, (Value & LEDMASK)) |
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172 | #define WarpV4_UserIO_PushB(BaseAddress) \ |
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173 | ((WARP_V4_USERIO_mReadSlaveReg1(BaseAddress, 0) & PBMASK) >> PB_OFFSET) |
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174 | #define WarpV4_UserIO_DipSw(BaseAddress) \ |
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175 | ((WARP_V4_USERIO_mReadSlaveReg1(BaseAddress, 0) & DIPMASK) >> DIP_OFFSET) |
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176 | |
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177 | #define WarpV4_UserIO_NumberMode_All(BaseAddress) \ |
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178 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | (LEFTHEX_NUM_MODE | MIDHEX_NUM_MODE | RIGHTHEX_NUM_MODE))) |
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179 | #define WarpV4_UserIO_NumberMode_LeftHex(BaseAddress) \ |
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180 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | LEFTHEX_NUM_MODE)) |
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181 | #define WarpV4_UserIO_NumberMode_MiddleHex(BaseAddress) \ |
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182 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | MIDHEX_NUM_MODE)) |
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183 | #define WarpV4_UserIO_NumberMode_RightHex(BaseAddress) \ |
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184 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) | RIGHTHEX_NUM_MODE)) |
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185 | |
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186 | #define WarpV4_UserIO_WriteNumber_LeftHex(BaseAddress, NumberTW, DecimalPoint) \ |
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187 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~LEFTHEX_NUM_VAL) | ((NumberTW & 0x0000000F) << LEFTHEX_OFFSET_NUM)) | ((DecimalPoint & 0x00000001) << (LEFTHEX_OFFSET_NUM+4)))) |
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188 | #define WarpV4_UserIO_WriteNumber_MiddleHex(BaseAddress, NumberTW, DecimalPoint) \ |
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189 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~MIDHEX_NUM_VAL) | ((NumberTW & 0x0000000F) << MIDHEX_OFFSET_NUM)) | ((DecimalPoint & 0x00000001) << (MIDHEX_OFFSET_NUM+4)))) |
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190 | #define WarpV4_UserIO_WriteNumber_RightHex(BaseAddress, NumberTW, DecimalPoint) \ |
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191 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~RIGHTHEX_NUM_VAL) | ((NumberTW & 0x0000000F) << RIGHTHEX_OFFSET_NUM)) | ((DecimalPoint & 0x00000001) << (RIGHTHEX_OFFSET_NUM+4)))) |
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192 | |
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193 | #define WarpV4_UserIO_ReadNumber_LeftHex(BaseAddress) \ |
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194 | ((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & LEFTHEX_NUM_VAL) >> LEFTHEX_OFFSET_NUM) |
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195 | #define WarpV4_UserIO_ReadNumber_MiddleHex(BaseAddress) \ |
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196 | ((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & MIDHEX_NUM_VAL) >> MIDHEX_OFFSET_NUM) |
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197 | #define WarpV4_UserIO_ReadNumber_RightHex(BaseAddress) \ |
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198 | ((WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & RIGHTHEX_NUM_VAL) >> RIGHTHEX_OFFSET_NUM) |
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199 | |
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200 | #define WarpV4_UserIO_LeftHex_Off(BaseAddress) \ |
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201 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) | (HEX_OFF_ON << LEFTHEX_OFFSET_NUM))) |
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202 | #define WarpV4_UserIO_MiddleHex_Off(BaseAddress) \ |
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203 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) | (HEX_OFF_ON << MIDHEX_OFFSET_NUM))) |
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204 | #define WarpV4_UserIO_RightHex_Off(BaseAddress) \ |
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205 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) | (HEX_OFF_ON << RIGHTHEX_OFFSET_NUM))) |
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206 | |
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207 | #define WarpV4_UserIO_LeftHex_On(BaseAddress) \ |
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208 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~(HEX_OFF_ON << LEFTHEX_OFFSET_NUM))) |
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209 | #define WarpV4_UserIO_MiddleHex_On(BaseAddress) \ |
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210 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~(HEX_OFF_ON << MIDHEX_OFFSET_NUM))) |
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211 | #define WarpV4_UserIO_RightHex_On(BaseAddress) \ |
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212 | WARP_V4_USERIO_mWriteSlaveReg2(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg2(BaseAddress, 0) & ~(HEX_OFF_ON << RIGHTHEX_OFFSET_NUM))) |
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213 | |
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214 | #define WarpV4_UserIO_Write_ExtraLeds(BaseAddress, Value) \ |
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215 | WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << IOEX_LEDS_OFFSET_RAW)) | ((Value & LEDMASK) << IOEX_LEDS_OFFSET_RAW))) |
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216 | #define WarpV4_UserIO_WriteRaw_LeftHex(BaseAddress, Value) \ |
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217 | WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << LEFTHEX_OFFSET_RAW)) | ((Value & LEDMASK) << LEFTHEX_OFFSET_RAW))) |
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218 | #define WarpV4_UserIO_WriteRaw_MiddleHex(BaseAddress, Value) \ |
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219 | WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << MIDHEX_OFFSET_RAW)) | ((Value & LEDMASK) << MIDHEX_OFFSET_RAW))) |
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220 | #define WarpV4_UserIO_WriteRaw_RightHex(BaseAddress, Value) \ |
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221 | WARP_V4_USERIO_mWriteSlaveReg3(BaseAddress, 0, ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) & ~(LEDMASK << RIGHTHEX_OFFSET_RAW)) | ((Value & LEDMASK) << RIGHTHEX_OFFSET_RAW))) |
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222 | |
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223 | #define WarpV4_UserIO_Read_ExtraLeds(BaseAddress) \ |
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224 | ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> IOEX_LEDS_OFFSET_RAW) & LEDMASK) |
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225 | #define WarpV4_UserIO_ReadRaw_LeftHex(BaseAddress) \ |
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226 | ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> LEFTHEX_OFFSET_RAW) & LEDMASK) |
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227 | #define WarpV4_UserIO_ReadRaw_MiddleHex(BaseAddress) \ |
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228 | ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> MIDHEX_OFFSET_RAW) & LEDMASK) |
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229 | #define WarpV4_UserIO_ReadRaw_RightHex(BaseAddress) \ |
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230 | ((WARP_V4_USERIO_mReadSlaveReg3(BaseAddress, 0) >> RIGHTHEX_OFFSET_RAW) & LEDMASK) |
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231 | |
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232 | #define WarpV4_UserIO_RawMode_All(BaseAddress) \ |
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233 | { \ |
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234 | WarpV4_UserIO_WriteRaw_LeftHex(BaseAddress, WarpV4_UserIO_ReadRaw_LeftHex(BaseAddress)); \ |
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235 | WarpV4_UserIO_WriteRaw_MiddleHex(BaseAddress, WarpV4_UserIO_ReadRaw_MiddleHex(BaseAddress)); \ |
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236 | WarpV4_UserIO_WriteRaw_RightHex(BaseAddress, WarpV4_UserIO_ReadRaw_RightHex(BaseAddress)); \ |
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237 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~(LEFTHEX_NUM_MODE | MIDHEX_NUM_MODE | RIGHTHEX_NUM_MODE))); \ |
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238 | } |
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239 | #define WarpV4_UserIO_RawMode_LeftHex(BaseAddress) \ |
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240 | { \ |
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241 | WarpV4_UserIO_WriteRaw_LeftHex(BaseAddress, WarpV4_UserIO_ReadRaw_LeftHex(BaseAddress)); \ |
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242 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~LEFTHEX_NUM_MODE)); \ |
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243 | } |
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244 | #define WarpV4_UserIO_RawMode_MiddleHex(BaseAddress) \ |
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245 | { \ |
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246 | WarpV4_UserIO_WriteRaw_MiddleHex(BaseAddress, WarpV4_UserIO_ReadRaw_MiddleHex(BaseAddress)); \ |
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247 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~MIDHEX_NUM_MODE)); \ |
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248 | } |
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249 | #define WarpV4_UserIO_RawMode_RightHex(BaseAddress) \ |
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250 | { \ |
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251 | WarpV4_UserIO_WriteRaw_RightHex(BaseAddress, WarpV4_UserIO_ReadRaw_RightHex(BaseAddress)); \ |
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252 | WARP_V4_USERIO_mWriteSlaveReg4(BaseAddress, 0, (WARP_V4_USERIO_mReadSlaveReg4(BaseAddress, 0) & ~RIGHTHEX_NUM_MODE)); \ |
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253 | } |
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254 | |
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255 | |
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256 | /************************** Function Prototypes ****************************/ |
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257 | |
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258 | |
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259 | |
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260 | #endif /** WARP_V4_USERIO_H */ |
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