1 | #include "wlan_mac_high_sw_config.h" |
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2 | |
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3 | #include "xil_cache.h" |
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4 | #include "wlan_platform_high.h" |
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5 | #include "w3_high.h" |
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6 | #include "w3_eth.h" |
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7 | #include "w3_uart.h" |
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8 | #include "w3_high_userio.h" |
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9 | #include "w3_userio_util.h" |
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10 | #include "w3_iic_eeprom.h" |
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11 | #include "w3_sw_intr.h" |
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12 | #include "w3_common.h" |
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13 | #include "wlan_platform_timer.h" |
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14 | #include "wlan_common_types.h" |
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15 | #include "wlan_platform_common.h" |
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16 | |
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17 | #include "wlan_mac_high.h" |
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18 | #include "wlan_mac_schedule.h" |
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19 | #include "wlan_exp_common.h" |
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20 | #include "wlan_exp_node.h" |
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21 | #include "wlan_exp_transport.h" |
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22 | #include "wlan_mac_queue.h" |
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23 | |
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24 | static const platform_high_dev_info_t w3_platform_high_dev_info = { |
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25 | .aux_bram_baseaddr = AUX_BRAM_BASEADDR, |
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26 | .aux_bram_size = AUX_BRAM_SIZE - PORTAL_ETH_BD_MEM_SIZE, |
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27 | .dram_baseaddr = WLAN_EXP_ETH_BD_MEM_HIGHADDR + 1, |
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28 | .dram_size = DRAM_SIZE - WLAN_EXP_ETH_BD_MEM_SIZE, |
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29 | .cdma_dev_id = PLATFORM_DEV_ID_CDMA, |
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30 | .mailbox_int_id = PLATFORM_INT_ID_MAILBOX, |
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31 | .timer_dur_us = TIMER_DUR_US, |
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32 | }; |
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33 | |
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34 | typedef struct _w3_node_info_t{ |
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35 | u64 fpga_dna; // FPGA DNA value, unique ID per chip |
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36 | s8 wlan_max_tx_power_dbm; // RF interface maximum transmit power |
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37 | s8 wlan_min_tx_power_dbm; // RF interface minimum transmit power |
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38 | } __attribute__((__packed__)) _w3_node_info_t; |
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39 | static _w3_node_info_t w3_node_info; |
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40 | ASSERT_TYPE_SIZE(_w3_node_info_t, 10); |
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41 | |
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42 | int _init_wlan_exp_node_info(); |
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43 | |
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44 | void wlan_platform_cpu_high_init() { |
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45 | |
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46 | Xil_AssertSetCallback((Xil_AssertCallback)wlan_assert_print); |
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47 | |
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48 | // Disable I and D cache |
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49 | Xil_DCacheDisable(); |
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50 | Xil_ICacheDisable(); |
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51 | |
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52 | // Enable exceptions - exceptions *must* be enabled on MicroBlaze |
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53 | // to handle unaligned memory accesses |
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54 | microblaze_enable_exceptions(); |
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55 | |
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56 | // Initialize HW platform |
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57 | wlan_platform_common_init(); |
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58 | |
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59 | // Fill in node info struct |
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60 | _init_wlan_exp_node_info(); |
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61 | |
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62 | return; |
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63 | |
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64 | } |
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65 | |
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66 | platform_high_dev_info_t wlan_platform_high_get_dev_info(){ |
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67 | return w3_platform_high_dev_info; |
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68 | } |
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69 | |
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70 | void wlan_platform_high_poll(){ |
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71 | } |
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72 | |
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73 | int wlan_platform_high_init() { |
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74 | int status; |
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75 | |
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76 | status = wlan_platform_intc_init(PLATFORM_DEV_ID_INTC); |
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77 | |
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78 | status |= wlan_timer_init(PLATFORM_DEV_ID_TIMER, TIMER_DUR_US*(TIMER_FREQ_HZ/1000000)); // 64 usec |
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79 | |
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80 | status |= wlan_timer_setup_interrupt(PLATFORM_INT_ID_TIMER, wlan_mac_schedule_poll); |
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81 | |
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82 | |
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83 | status |= w3_uart_init(); |
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84 | status |= w3_uart_setup_interrupt(); |
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85 | |
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86 | status |= w3_high_userio_init(); |
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87 | status |= w3_high_userio_setup_interrupt(); |
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88 | |
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89 | status |= w3_sw_intr_init(); |
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90 | |
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91 | // Initialize Ethernet in wlan_platform |
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92 | status |= w3_wlan_platform_ethernet_init(); |
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93 | |
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94 | // Set stack protection addresses |
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95 | // Set stack protection addresses |
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96 | // Linker sets these variables at build time |
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97 | extern int _stack_end; ///< Start of the stack (stack counts backwards) |
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98 | extern int __stack; ///< End of the stack |
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99 | mtshr(&__stack); |
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100 | mtslr(&_stack_end); |
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101 | |
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102 | return status; |
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103 | } |
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104 | |
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105 | void wlan_platform_free_queue_entry_notify(){ |
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106 | #if WLAN_SW_CONFIG_ENABLE_ETH_BRIDGE |
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107 | w3_wlan_platform_ethernet_free_queue_entry_notify(); |
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108 | #endif |
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109 | } |
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110 | |
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111 | |
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112 | void wlan_platform_high_userio_disp_status(userio_disp_high_status_t status, int status_param){ |
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113 | |
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114 | static application_role_t application_role = APPLICATION_ROLE_UNKNOWN; |
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115 | |
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116 | switch(status){ |
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117 | |
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118 | case USERIO_DISP_STATUS_IDENTIFY: { |
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119 | blink_hex_display(25, 200000); |
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120 | } break; |
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121 | |
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122 | case USERIO_DISP_STATUS_APPLICATION_ROLE: { |
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123 | application_role = (application_role_t)status_param; |
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124 | |
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125 | if(application_role == APPLICATION_ROLE_AP){ |
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126 | // Set Periodic blinking of hex display (period of 500 with min of 2 and max of 400) |
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127 | set_hex_pwm_period(500); |
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128 | set_hex_pwm_min_max(2, 400); |
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129 | enable_hex_pwm(); |
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130 | } |
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131 | } break; |
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132 | |
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133 | case USERIO_DISP_STATUS_MEMBER_LIST_UPDATE: { |
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134 | if(application_role == APPLICATION_ROLE_AP){ |
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135 | write_hex_display_with_pwm((u8)status_param); |
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136 | } else { |
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137 | write_hex_display((u8)status_param); |
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138 | } |
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139 | |
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140 | } break; |
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141 | |
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142 | case USERIO_DISP_STATUS_WLAN_EXP_CONFIGURE: { |
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143 | |
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144 | if( status_param ){ |
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145 | set_hex_display_right_dp(1); |
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146 | } else { |
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147 | set_hex_display_right_dp(0); |
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148 | } |
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149 | } break; |
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150 | |
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151 | case USERIO_DISP_STATUS_CPU_ERROR: { |
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152 | |
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153 | u32 error_code = (u32)status_param; |
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154 | if (status_param != WLAN_ERROR_CPU_STOP) { |
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155 | // Print error message |
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156 | xil_printf("\n\nERROR: CPU is halting with error code: E%X\n\n", (error_code & 0xF)); |
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157 | |
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158 | // Set the error code on the hex display |
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159 | set_hex_display_error_status(error_code & 0xF); |
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160 | |
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161 | // Enter infinite loop blinking the hex display |
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162 | blink_hex_display(0, 250000); |
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163 | } else { |
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164 | // Stop execution |
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165 | while (1) {}; |
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166 | } |
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167 | |
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168 | } break; |
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169 | |
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170 | default: |
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171 | break; |
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172 | } |
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173 | |
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174 | |
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175 | return; |
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176 | |
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177 | } |
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178 | |
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179 | #if WLAN_SW_CONFIG_ENABLE_WLAN_EXP |
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180 | int wlan_platform_wlan_exp_process_node_cmd(cmd_resp_hdr_t* cmd_hdr, eth_tx_queue_buffer_t* eth_tx_queue_buffer, u8* cmd_processed){ |
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181 | |
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182 | // |
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183 | // IMPORTANT ENDIAN NOTES: |
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184 | // - command |
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185 | // - header - Already endian swapped by the framework (safe to access directly) |
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186 | // - args - Must be endian swapped as necessary by code (framework does not know the contents of the command) |
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187 | // - response |
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188 | // - header - Will be endian swapped by the framework (safe to write directly) |
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189 | // - args - Must be endian swapped as necessary by code (framework does not know the contents of the response) |
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190 | // |
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191 | |
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192 | u32 resp_sent = NO_RESP_SENT; |
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193 | u32 cmd_id = CMD_TO_CMDID(cmd_hdr->cmd); |
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194 | |
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195 | // Segment 0 length includes a fully formed command response header |
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196 | // because one was created with default values suitable for a responseless |
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197 | // acknowledgment. |
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198 | cmd_resp_hdr_t* resp_hdr = (cmd_resp_hdr_t*)(eth_tx_queue_buffer->seg0 |
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199 | + eth_tx_queue_buffer->seg0_len |
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200 | - sizeof(cmd_resp_hdr_t)); |
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201 | |
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202 | u32* cmd_args_32 = (u32*)((u8*)cmd_hdr + sizeof(cmd_resp_hdr_t)); |
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203 | u32* resp_args_32 = (u32*)((u8*)resp_hdr + sizeof(cmd_resp_hdr_t)); |
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204 | u32 resp_index = 0; |
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205 | |
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206 | // NOTE: Response header cmd, length, and num_args fields have already been initialized. |
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207 | // |
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208 | |
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209 | *cmd_processed = 1; |
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210 | |
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211 | switch(cmd_id){ |
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212 | default: |
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213 | *cmd_processed = 0; |
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214 | break; |
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215 | //--------------------------------------------------------------------- |
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216 | case CMDID_DEV_EEPROM: { |
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217 | |
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218 | |
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219 | // Read / Write values from / to EEPROM |
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220 | // |
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221 | // Write Message format: |
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222 | // cmd_args_32[0] Command == CMD_PARAM_WRITE_VAL |
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223 | // cmd_args_32[1] EEPROM (0 = ON_BOARD / 1 = FMC) |
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224 | // cmd_args_32[2] Address |
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225 | // cmd_args_32[3] Length (Number of u8 bytes to write) |
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226 | // cmd_args_32[4:] Values to write (Length u32 values each containing a single byte to write) |
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227 | // Response format: |
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228 | // resp_args_32[0] Status |
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229 | // |
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230 | // Read Message format: |
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231 | // cmd_args_32[0] Command == CMD_PARAM_READ_VAL |
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232 | // cmd_args_32[1] EEPROM Device (1 = ON_BOARD / 0 = FMC) |
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233 | // cmd_args_32[2] Address |
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234 | // cmd_args_32[3] Length (number of u8 bytes to read) |
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235 | // Response format: |
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236 | // resp_args_32[0] Status |
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237 | // resp_args_32[1] Length (Number of u8 bytes read) |
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238 | // resp_args_32[2:] EEPROM values (Length u32 values each containing a single byte read) |
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239 | // |
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240 | #define EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_ONBOARD_BASEADDR |
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241 | #define FMC_EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_FMC_BASEADDR |
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242 | |
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243 | u32 eeprom_idx; |
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244 | int eeprom_status; |
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245 | u8 byte_to_write; |
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246 | u32 status = CMD_PARAM_SUCCESS; |
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247 | u32 msg_cmd = Xil_Ntohl(cmd_args_32[0]); |
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248 | u32 eeprom_device = Xil_Ntohl(cmd_args_32[1]); |
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249 | u32 eeprom_addr = (Xil_Ntohl(cmd_args_32[2]) & 0xFFFF); |
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250 | u32 eeprom_length = Xil_Ntohl(cmd_args_32[3]); |
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251 | u32 use_default_resp = WLAN_EXP_TRUE; |
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252 | u32 eeprom_ba = EEPROM_BASEADDR; |
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253 | u32 max_resp_len = wlan_exp_transport_get_max_pkt_words(); |
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254 | |
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255 | // Select EEPROM device |
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256 | if (eeprom_device) { |
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257 | eeprom_ba = EEPROM_BASEADDR; |
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258 | } else { |
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259 | #if FMC_EEPROM_BASEADDR |
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260 | eeprom_ba = FMC_EEPROM_BASEADDR; |
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261 | #else |
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262 | wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "FMC EEPROM not supported\n"); |
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263 | msg_cmd = CMD_PARAM_RSVD; |
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264 | #endif |
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265 | } |
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266 | |
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267 | switch (msg_cmd) { |
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268 | case CMD_PARAM_WRITE_VAL: |
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269 | wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, "Write EEPROM:\n"); |
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270 | wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Addr: 0x%08x\n", eeprom_addr); |
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271 | wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Len: %d\n", eeprom_length); |
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272 | |
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273 | // Don't bother if length is clearly bogus |
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274 | if(eeprom_length < max_resp_len) { |
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275 | for (eeprom_idx = 0; eeprom_idx < eeprom_length; eeprom_idx++) { |
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276 | // Endian swap payload and extract the byte to write |
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277 | byte_to_write = (Xil_Ntohl(cmd_args_32[eeprom_idx + 4]) & 0xFF); |
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278 | |
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279 | // Write the byte and break if there was an EEPROM failure |
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280 | eeprom_status = iic_eeprom_write_byte(eeprom_ba, (eeprom_addr + eeprom_idx), byte_to_write, XPAR_CPU_ID); |
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281 | |
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282 | if (eeprom_status == IIC_EEPROM_FAILURE) { |
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283 | wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM write failed at byte %d\n", eeprom_idx); |
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284 | status = CMD_PARAM_ERROR; |
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285 | break; |
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286 | } |
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287 | } |
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288 | } else { |
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289 | wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM write longer than %d bytes\n", max_resp_len); |
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290 | status = CMD_PARAM_ERROR; |
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291 | } |
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292 | break; |
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293 | |
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294 | case CMD_PARAM_READ_VAL: |
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295 | // There's a chicken and egg problem in this command trying to use the |
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296 | // wlan_exp_add_u32_resp_arg() utility. The first word, status, might |
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297 | // become CMD_PARAM_ERROR as we are well into reading bytes from the |
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298 | // EEPROM. To use the wlan_exp_add_u32_resp_arg() function, we need to |
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299 | // know the final value of the first word before writing any other words |
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300 | // to the response. We will simply leave the "old" resp_index method of |
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301 | // writing a response. |
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302 | wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, "Read EEPROM:\n"); |
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303 | wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Addr: 0x%08x\n", eeprom_addr); |
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304 | wlan_exp_printf(WLAN_EXP_PRINT_INFO, print_type_node, " Len: %d\n", eeprom_length); |
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305 | |
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306 | if (eeprom_length < max_resp_len) { |
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307 | // Don't set the default response |
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308 | use_default_resp = WLAN_EXP_FALSE; |
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309 | |
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310 | for (eeprom_idx = 0; eeprom_idx < eeprom_length; eeprom_idx++) { |
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311 | // Read the byte and break if there was an EEPROM failure |
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312 | eeprom_status = iic_eeprom_read_byte(eeprom_ba, (eeprom_addr + eeprom_idx), XPAR_CPU_ID); |
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313 | |
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314 | if (eeprom_status == IIC_EEPROM_FAILURE) { |
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315 | wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM write failed at byte %d\n", eeprom_idx); |
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316 | status = CMD_PARAM_ERROR; |
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317 | break; |
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318 | } |
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319 | |
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320 | // Add the byte read and Endian swap the payload |
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321 | // - This modified the output Ethernet packet but does not update the resp_index variable |
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322 | resp_args_32[resp_index + eeprom_idx + 2] = Xil_Htonl(eeprom_status & 0xFF); |
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323 | } |
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324 | |
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325 | // Add length argument to response |
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326 | resp_args_32[resp_index++] = Xil_Htonl(status); |
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327 | resp_args_32[resp_index++] = Xil_Htonl(eeprom_idx); |
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328 | resp_index += eeprom_idx; // Update response index for all EEPROM bytes |
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329 | resp_hdr->length += (resp_index * sizeof(resp_args_32)); |
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330 | eth_tx_queue_buffer->seg0_len += (resp_index * sizeof(u32)); |
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331 | resp_hdr->num_u32_args = resp_index; |
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332 | |
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333 | } else { |
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334 | wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "CMDID_DEV_EEPROM read longer than %d bytes\n", max_resp_len); |
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335 | status = CMD_PARAM_ERROR; |
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336 | } |
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337 | break; |
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338 | |
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339 | case CMD_PARAM_RSVD: |
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340 | status = CMD_PARAM_ERROR; |
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341 | break; |
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342 | |
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343 | default: |
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344 | wlan_exp_printf(WLAN_EXP_PRINT_ERROR, print_type_node, "Unknown command for 0x%6x: %d\n", cmd_id, msg_cmd); |
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345 | status = CMD_PARAM_ERROR; |
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346 | break; |
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347 | } |
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348 | |
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349 | if (use_default_resp) { |
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350 | // Send default response |
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351 | wlan_exp_add_u32_resp_arg(eth_tx_queue_buffer, resp_hdr, status); |
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352 | } |
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353 | |
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354 | } |
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355 | |
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356 | break; |
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357 | |
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358 | } |
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359 | |
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360 | return resp_sent; |
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361 | |
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362 | } |
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363 | #endif |
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364 | |
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365 | int wlan_platform_high_copy_info(u8* dest){ |
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366 | memcpy(dest, &w3_node_info, sizeof(_w3_node_info_t)); |
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367 | return sizeof(_w3_node_info_t); |
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368 | } |
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369 | |
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370 | int _init_wlan_exp_node_info(){ |
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371 | |
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372 | wlan_mac_hw_info_t hw_info = wlan_platform_get_hw_info(); |
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373 | |
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374 | xil_printf("Initializing node Serial Number : %s-%05d\n", hw_info.serial_number_prefix, hw_info.serial_number); |
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375 | |
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376 | //FIXME: Did I get the endianness right on this? |
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377 | w3_node_info.fpga_dna = (((u64)w3_eeprom_read_fpga_dna(EEPROM_BASEADDR, 1)) << 32) + (u64)w3_eeprom_read_fpga_dna(EEPROM_BASEADDR, 0); |
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378 | w3_node_info.wlan_max_tx_power_dbm = TX_POWER_MAX_DBM; |
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379 | w3_node_info.wlan_min_tx_power_dbm = TX_POWER_MIN_DBM; |
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380 | return WLAN_SUCCESS; |
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381 | } |
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