Changes between Version 1 and Version 2 of HardwareUsersGuides/CM-PLL/Configuration
- Timestamp:
- Jan 24, 2015, 9:20:20 PM (9 years ago)
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HardwareUsersGuides/CM-PLL/Configuration
v1 v2 4 4 5 5 The CM-PLL board includes a 6-position DIP switch to configure various functions. 6 7 == Reference Clock Output == 8 9 Switch 1 controls the reference clock output pin on the external header: 10 11 ||= Switches =||= Configuration =|| 12 || [[Image(wiki:HardwareUsersGuides/CM-PLL/files:dipsw_refout_0.png, nolink)]] || '''Disables''' the reference clock output. Use this configuration when no cable is connected to the '''OUT''' external header. || 13 || [[Image(wiki:HardwareUsersGuides/CM-PLL/files:dipsw_refout_1.png, nolink)]] || '''Enables''' the reference clock output. Use this configuration when a cable is connected to the '''OUT''' external header and the downstream CM-PLL has selected its external header reference clock input. || 6 14 7 15 == Reference Clock Source == … … 14 22 || [[Image(wiki:HardwareUsersGuides/CM-PLL/files:dipsw_refclk_10.png, nolink)]] || Selects the '''Local WARP v3 Oscillator''' reference clock input. Use this configuration when no external reference clock is required. This configuration should be used at the first node in a daisy chain of WARP v3 kits with CM-PLL modules. || 15 23 24 == Reference Clock Source == 25 26 Switches 4-6 are connected to FPGA I/O. The FPGA design should read these switch values to configure clock modes at boot. Refer to the [wiki:cores/w3_clock_controller w3_clock_controller] documentation for details on the default use of these switches in the reference designs for WARP v3.
