Version 11 (modified by murphpo, 17 years ago) (diff) |
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Register bits [31:16]
Register bits [15:0]
Rx_ControlBits
Address: 0x0
Dir: Read/Write
Fields:
CFO_USE_LONGCORR
(Bit 12) Enables the use of the long correlator to control the timing of the carrier frequency offset estimation based on the long training symbols. This must be set to 1 for normal operation.
CFO_USE_STS
(Bit 11) Enables carrier frequency offset estimation based on the preamble's short training symbols. When using high-quality oscillators, this can be disabled to improve CFO estimation performance.
CFO_USE_LTS
(Bit 10) Enables carrier frequency offset estimation based on the preamble's long training symbols. Must be set to 1 for normal operation.
CFO_BYPASS
(Bit 9) When set to 1, CFO correction is bypassed. This should only be used when driving two nodes from a common reference clock during PHY debugging.
INT_PKTDET_EN
(Bit 8) Enables the internal packet detection block. This should only be used when debugging the PHY over a wire when the external packet detector is not being used.
EXT_PKTDET_EN
(Bit 7) Enables external packet detection via the rx_extpktdet top-level port
REQ_SHORT_CORR
(Bit 6) Requires either internal or external packet detection in order to begin processing a packet. When disabled, the receiver will begin processing packets when trigged only by the long correlator.
REQ_TWO_LONG_CORR
(Bit 5) Requires two threshold crossings from the long correlator, spaced exactly 64 cycles apart. When enaled, this makes packet detection more robust at the cost of more false negative detections.
SISO_MODE
(Bit 4) Enables single-antenna (SISO) mode in the receiver. In this mode, only packets transmitted in SISO mode will be properly received.
DYN_PKT_LENGTHS
(Bit 2) Enables dynamic packet lengths. This should be 1 for normal operation. When disabled, the receiver assumes every packet is a fixed length. This is useful during PHY debugging and BER testing.
REQ_LONG_CORR
(Bit 1) Requires a threshold crossing in the long correlator for packet detection. This must be one for reliable operation.
BER_RESET
(Bit 0) When enabled, the BER calculation engine is held in reset. This should be 0 only during BER testing.
Rx_GlobalReset
Address: 0x4
Dir: Read/Write
Fields:
RX_RESET
(Bit 0) Global reset for the receiver state machines. When set to 1, all state in the packet detection, PHY processing, packet construction and interrupt blocks is cleared. This reset does not clear the values of OPB regsters.
Rx_OFDM_SymbolCounts
Address: 0x8
Dir: Read/Write
Fields:
NUM_BASERATE_SYMS
(BitS 31:16 - UFix16_0) This integer sets the number of base rate symbols the receiver should process with each incoming packet. See the OFDM frame format documentation for more information.
NUM_TRAINING_SYMS
(BitS 15:0 - UFix16_0) This integer sets the number of training symbol periods at the receiver. This value corresponds to the number of OFDM symbol periods dedicated to training. In MIMO mode, the training symbols are divided between antennas, orthogally in time. In SISO mode, every training period is used for estimating the single channel. See the OFDM frame format documentation for more information.
Rx_PktDet_Delay
Address: 0xC
Dir: Read/Write
Fields:
NUM_TRAINING_SYMS
(BitS 6:0 - UFix7_0) This integer sets the delay inserted between the course packet detection signal and the start of receiver processing. This delay should correspond to the time difference between packet detection and the start of the preamble's fourth short training symbol.
Rx_PktDet_LongCorr_Params
Address: 0x10
Dir: Read/Write
Fields:
CORR_SET_TIMING
(Bits 31:16 - UFix16_0) This integer sets sample index used when a long correlation event occurs. The receiver uses a large counter to track packet timing. This counter increments with each sample, starting with course packet detection. When the long correlator crosses its threshold, the counter is set to this value.
CORR_THRESHOLD
(Bits 15:0 - UFix16_0) This integer sets the long correlation threshold used during fine packet detection and symbol timing.