| 3 | | The WARP MIMO OFDM core is an OPB-compliant peripheral core, created using our [wiki:sysgen2opb sysgen2opb] tool. The core utilizes sysgen2opb's shared memory block support, which creates memory blocks in the core which are directly mapped into the address space of the host processor. The OFDM core has four of these shared memory blocks, which are desribed in detail below. |
| 4 | | |
| 5 | | = Packet Buffers = |
| 6 | | The first two shared memory blocks function as packet buffers. The OFDM core uses separate buffers for the transmit and receive paths. |
| 7 | | |
| 8 | | == Transmit Packet Buffer == |
| 9 | | The transmit packet buffer is the memory block used for a packet which the user application needs to send over the air. This memory space is a write-only memory block with 4096 bytes of storage (0x1000 bytes). The user application must write an integral number of 32-bit words comprising a packet before enabling transmission. The memory block is accessed by directly writing to the base address of the block's address space. The OFDM core's driver provides a C macro ([source:/PlatformSupport/CustomPeripherals/drivers/ofdm_TxRx_mimo_opbw_v1_07_a/src/ofdm_TxRx_mimo.h@L#L141 ofdm_TxRx_mimo_SMWO_TxPktBuffer_OFFSET]) which specifies this address relative to the core's base address. The core's base address is provided as a C macro by the EDK during compilation and will usually be named XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR. |
| 10 | | |
| 11 | | This C-code example below illustrates one way of interfacing to the transmit packet buffer. This code is adapted from the OFDM core's driver ([source:/PlatformSupport/CustomPeripherals/drivers/ofdm_TxRx_mimo_opbw_v1_07_a/src/ofdm_Tx_mimo.h@L#L44 ofdm_Tx_mimo.h]). |
| 12 | | {{{ |
| 13 | | #!c |
| 14 | | memcpy ( |
| 15 | | (unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR + ofdm_TxRx_mimo_SMWO_TxPktBuffer_OFFSET), |
| 16 | | (unsigned int*)myPacketPointer, |
| 17 | | myPacketLength |
| 18 | | ); |
| 19 | | }}} |
| 20 | | |
| 21 | | |
| 22 | | |
| 23 | | == Receive Packet Buffer == |
| 24 | | The receive packet buffer is the memory block used by the user application for reading a packet which which has been received over the air. This memory space is a read-only memory block with 4096 bytes of storage (0x1000 bytes). The user application must read an integral number of 32-bit words comprising a packet. The memory block is accessed by directly read the base address of the block's address space. The OFDM core's driver provides a C macro ([source:/PlatformSupport/CustomPeripherals/drivers/ofdm_TxRx_mimo_opbw_v1_07_a/src/ofdm_TxRx_mimo.h@L#L141 ofdm_TxRx_mimo_SMRO_RxPktBuffer_OFFSET]) which specifies this address relative to the core's base address. The core's base address is provided as a C macro by the EDK during compilation and will usually be named XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR. |
| 25 | | |
| 26 | | This C-code example below illustrates one way of interfacing to the receive packet buffer. This code is adapted from the OFDM core's driver ([source:/PlatformSupport/CustomPeripherals/drivers/ofdm_TxRx_mimo_opbw_v1_07_a/src/ofdm_Rx_mimo.h@L#L55 ofdm_Rx_mimo.h]). |
| 27 | | {{{ |
| 28 | | #!c |
| 29 | | memcpy ( |
| 30 | | (unsigned int*)myPacketPointer, |
| 31 | | (unsigned int*)(XPAR_OFDM_TXRX_MIMO_OPBW_0_BASEADDR + ofdm_TxRx_mimo_SMRO_RxPktBuffer_OFFSET), |
| 32 | | myPacketLength |
| 33 | | ); |
| 34 | | }}} |
| | 3 | The WARP MIMO OFDM core is an OPB-compliant peripheral core, created using our [wiki:sysgen2opb sysgen2opb] tool. The core utilizes sysgen2opb's shared memory block support, which creates memory blocks in the core which are directly mapped into the address space of the host processor. The OFDM core has three of these shared memory blocks, which are desribed in detail below. |
