1 | <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"> |
---|
2 | <html xmlns="http://www.w3.org/1999/xhtml"> |
---|
3 | <head> |
---|
4 | <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> |
---|
5 | <meta name="generator" content="ScreenSteps http://www.screensteps.com/" /> |
---|
6 | <title>Base System Builder - FPGA Board v1.2</title> |
---|
7 | <link href="../neutral.css" media="screen" rel="stylesheet" type="text/css" /> |
---|
8 | </head> |
---|
9 | |
---|
10 | <body class="lucida"> |
---|
11 | <div id="wrapper"> |
---|
12 | <div id="header"> |
---|
13 | <a id="logo" href="http://warp.rice.edu/trac/"><img src="http://warp.rice.edu/images/warpLogo.jpg" alt="Rice University WARP - Wireless Open-Access Research Platform" height="45" width="285" /></a> |
---|
14 | </div> |
---|
15 | <div id="mainnav" class="nav"> |
---|
16 | <ul> |
---|
17 | <li class="first active"><a href="/trac/wiki">Home</a></li><li><a href="/forums">Forums</a></li><li><a href="/trac/browser">Browse Source</a></li> |
---|
18 | </ul> |
---|
19 | </div> |
---|
20 | <div id="LessonContent"> |
---|
21 | <div class="LessonHeader"> |
---|
22 | <h1 class="LessonTitle">Base System Builder - FPGA Board v1.2</h1> |
---|
23 | </div> |
---|
24 | <div class="summary"> |
---|
25 | <p>This section describes the process of launching XPS and creating a simple hardware/software platform using Base System Builder. This section of the tutorial is specifically created for FPGA Board v1.2. Once you complete this section, skip to <strong>XPS Intro - Implementing the hardware design</strong>. Skip this section if you have FPGA Board v2.2.</p> |
---|
26 | </div> |
---|
27 | |
---|
28 | <div id="step_1" class="lessonStep top"> |
---|
29 | |
---|
30 | <div class="image"> |
---|
31 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215322293367.png" width="558" height="211"> |
---|
32 | </div> <p>Launch the Xilinx Platform Studio application.</p> |
---|
33 | </div> |
---|
34 | <div class="clear"></div> |
---|
35 | <div id="step_2" class="lessonStep top"> |
---|
36 | |
---|
37 | <div class="image"> |
---|
38 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215322383765.png" width="369" height="303"> |
---|
39 | </div> <p>Select Base System Builder to create a new project.</p> |
---|
40 | </div> |
---|
41 | <div class="clear"></div> |
---|
42 | <div id="step_3" class="lessonStep top"> |
---|
43 | |
---|
44 | <div class="image"> |
---|
45 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/BSBPath.png" width="407" height="245"> |
---|
46 | </div> <p>Enter a path for your project. Two key requirements:<br /> |
---|
47 | -The project file must be named 'system.xmp'<br /> |
---|
48 | -The project file must be saved to a folder with no spaces in its path - "C:\Documents and Settings\user\" will not work!</p> |
---|
49 | </div> |
---|
50 | <div class="clear"></div> |
---|
51 | <div id="step_4" class="lessonStep top"> |
---|
52 | |
---|
53 | <div class="image"> |
---|
54 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215323301511.png" width="508" height="725"> |
---|
55 | </div> <p>Choose the option for a new design.</p> |
---|
56 | </div> |
---|
57 | <div class="clear"></div> |
---|
58 | <div id="step_5" class="lessonStep top"> |
---|
59 | |
---|
60 | <div class="image"> |
---|
61 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324564466.png" width="508" height="725"> |
---|
62 | </div> <p>Base System Builder supports many development boards, including the WARP hardware platform. For this exercise, choose the board named 'WARP FPGA Board' and select revision 'FPGA 1.2'.</p> |
---|
63 | </div> |
---|
64 | <div class="clear"></div> |
---|
65 | <div id="step_6" class="lessonStep top"> |
---|
66 | |
---|
67 | <div class="image"> |
---|
68 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215323375118.png" width="509" height="725"> |
---|
69 | </div> <p>The Xilinx EDK supports two embedded processors. The PowerPC processor is a "hard" processor core, embedded in the fabric of the Virtex-II Pro FPGA on the WARP FPGA board. MicroBlaze is a "soft" processor core, implemented in the FPGA fabric itself. For this exercise (and all WARP designs generally), select the PowerPC core.</p> |
---|
70 | </div> |
---|
71 | <div class="clear"></div> |
---|
72 | <div id="step_7" class="lessonStep top"> |
---|
73 | |
---|
74 | <div class="image"> |
---|
75 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/DOCM.png" width="507" height="705"> |
---|
76 | </div> <p>The clocking and memory architectures for EDK designs are very flexible. Base System Builder supports some simple clock/memory configurations. In more sophisticated designs, the clocking and memory options can be further customized by hand. For this exercise, select the clock frequencies and memory sizes shown above. </p> |
---|
77 | </div> |
---|
78 | <div class="clear"></div> |
---|
79 | <div id="step_8" class="lessonStep top"> |
---|
80 | |
---|
81 | <div class="image"> |
---|
82 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215530729043.png" width="509" height="725"> |
---|
83 | </div> <p>The next few screens present a list of available I/O devices. Each device corresponds to an off-chip interface on the WARP FPGA board. Each device can be enaled/disabled using its checkbox. For this exercise, choose the peripherals as follows:</p> |
---|
84 | |
---|
85 | |
---|
86 | <p><strong>Enabled:</strong><br /> |
---|
87 | - User I/O (with 'Use interrupt enabled)<br /> |
---|
88 | - rs232 (configured for 57600 bps)</p> |
---|
89 | |
---|
90 | |
---|
91 | <p><strong>Disabled:</strong><br /> |
---|
92 | - sysace_compactflash<br /> |
---|
93 | - eeprom_controller<br /> |
---|
94 | - Ethernet_MAC<br /> |
---|
95 | - user_io_board_controller_slot1<br /> |
---|
96 | - SRAM0 / SRAM1</p> |
---|
97 | </div> |
---|
98 | <div class="clear"></div> |
---|
99 | <div id="step_9" class="lessonStep top"> |
---|
100 | |
---|
101 | <div class="image"> |
---|
102 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324622800.png" width="509" height="725"> |
---|
103 | </div> |
---|
104 | </div> |
---|
105 | <div class="clear"></div> |
---|
106 | <div id="step_10" class="lessonStep top"> |
---|
107 | |
---|
108 | <div class="image"> |
---|
109 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324643209.png" width="507" height="723"> |
---|
110 | </div> <p>After configuring off-chip devices, you now configure on-chip peripheral cores. By default, an internal RAM block is enabled. For this exercise, click 'Remove' to omit this core from the design.</p> |
---|
111 | </div> |
---|
112 | <div class="clear"></div> |
---|
113 | <div id="step_11" class="lessonStep top"> |
---|
114 | |
---|
115 | <div class="image"> |
---|
116 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631264826.png" width="509" height="725"> |
---|
117 | </div> <p>For user applications running in the PowerPC processor, the EDK tools can map the WARP FPGA board's serial port (the core named 'rs232' here) to the STDIN/STDOUT conventions. This allows funcitons like printf() to work normally, using an external terminal emulator as the PowerPC's display and keyboard.</p> |
---|
118 | |
---|
119 | |
---|
120 | <p>XPS can also create sample software projects which exercise the memory and peripheral devices in your hardware design. For this exercise, disable both example proejcts (you'll create a new software project later).</p> |
---|
121 | </div> |
---|
122 | <div class="clear"></div> |
---|
123 | <div id="step_12" class="lessonStep top"> |
---|
124 | |
---|
125 | <div class="image"> |
---|
126 | <img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215324692690.png" width="507" height="725"> |
---|
127 | </div> <p>Base System Builder assigns default memory addresses to each memory and memory-mapped peripheral device. The addresses in your project may vary from those shown here. In general, the defaults selected by BSB work fine.</p> |
---|
128 | </div> |
---|
129 | <div class="clear"></div> |
---|
130 | <div id="step_13" class="lessonStep top"> |
---|
131 | |
---|
132 | <div class="image"> |
---|
133 | <a href="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631451171_lg.png" class="image" target="_blank"><img src="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631451171.png" width="580" height="310"></a> |
---|
134 | <div class="caption"><a href="images/Base_System_Builder_-_FPGA_Board_v1/media_1215631451171_lg.png" target="_blank">Zoom</a></div> |
---|
135 | </div> <p>When Base System Builder finishes, XPS will open the resulting project. The remaining sections of this exercise describe how to use this interface to customize and test your hardware & software platform.</p> |
---|
136 | </div> |
---|
137 | <div class="clear"></div> |
---|
138 | |
---|
139 | </div> |
---|
140 | <div id="lessonNavigation"> |
---|
141 | <table> |
---|
142 | <tr> |
---|
143 | <td class="lessonNav_Left"><a href="Requirements___Setup.html"><< Requirements & Setup</a></td> |
---|
144 | <td class="lessonNav_TOC"><a href="../XPS_Intro.html">Top</a></td> |
---|
145 | <td class="lessonNav_Right"><a href="Base_System_Builder_-_FPGA_Board_v2.html">Base System Builder - FPGA Board v2.2 >></a> </td> |
---|
146 | </tr> |
---|
147 | </table> |
---|
148 | </div> |
---|
149 | </div> |
---|
150 | </body> |
---|
151 | </html> |
---|