MAC Layer Development on WARP

Within the Xilinx Virtex-II Pro lies two PowerPC 405 processors. Currently, we use only one of these cores. The PPC has two primary functions in our system: Peripheral control and MAC-level processing.

Peripheral Control

The commercial and custom peripherals that make up the designs need C-code drivers to wrap around register reads and writes. For our systems, these tasks are divided between the peripheral drivers and an additional layer of abstraction called WARPPHY.

MAC-level Processing

Above the control sublayer is the processing necessary to give the system MAC-level behavior like exponential backoffs and carrier-sensing. These tasks are divided between the user-level MAC code (such as CSMA MAC) and a MAC framework called WARPMAC.

What we provide

In general, user-level MAC algorithms are connected to the underlying hardware via WARPMAC, which provides MAC feature commonalities to the user. For derivatives of common random-access algorithms, the user may not need to modify any of the underlying layers. However, for more clean-slate designs, additional hardware functionality may be required. The WARPMAC framework and WARPPHY interface were designed with this in mind. Modification of these sublayers to support additional features is welcome. The relationship between user-level MAC algorithms and the WARP platform support is described in more detail in our publication.

Requirements for MAC

To use the existing infrastructure as-is, the MAC layer must be random-access. That being said, scheduled-access MAC algorithms are very possible and have had some success already on WARP. The primary example of a MAC layer that is well-matched to the underlying infrastructure is CSMAMAC, our carrier-sensing random-access MAC layer. Derivatives of this MAC are found in the lab exercises.


Reference Design

The primary reference design uses an OFDM PHY and CSMA MAC.

Last modified 14 years ago Last modified on Feb 7, 2008, 12:58:23 PM