Physical Layer Development on WARP

The Xilinx Virtex-II Pro on the FPGA board is well-suited to the DSP heavy-lifting required by modern physical layer designs. This page is intended to outline some basic requirements that users' PHYs must meet in order to interface with the WARP Platform Support Packages.

What we provide

Requirements for PHY

In general, it is impossible to specify in full generality the information that must be shared between any possible MAC layer with any possible PHY. For example, novel cross-layer designs will require much more sharing of state information than present in the reference design. However, a large class of PHY-MAC interfaces will share certain behaviors like triggers to begin transmission and header copy commands. With that in mind, we have created WARPPHY as an additional layer of abstraction to the drivers of our custom peripherals. New PHYs need to recreate this to provide a common interface to existing MAC layers.


Reference Design

The primary reference design uses an OFDM PHY and CSMA MAC.

Last modified 14 years ago Last modified on Sep 3, 2008, 12:48:43 AM