CM-PLL Clock Module: WARP v3 I/O
The CM-PLL connects to the WARP v3 clock module header. The clock module header provides connections to power, clock I/O and FPGA I/O. The use of these signals on the CM-PLL module is detailed below.
The CM-PLL header (J4) connects to the WARP v3 clock module header (J6). The schematics for both boards use the pin numbering scheme from the Samtec LSHM connector documentation. When mated, the mapping of connected pins is 1:2, 2:1, 3:4, 4:3, etc. The table below lists all signal pins on the clock module header and how each is mapped to circuits on the CM-PLL. Power and ground pins are omitted from this table. Refer to the schematics for more details.
CM-PLL J4 Pin | CM-PLL Net | W3 J6 Pin | W3 Net | FPGA Pin | Description |
---|---|---|---|---|---|
8 | DIPSW_0 | 7 | CLKHDR_CTRL12 | V30 | CM-PLL DIP Switch (position 4) |
10 | DIPSW_1 | 9 | CLKHDR_CTRL13 | R34 | CM-PLL DIP Switch (position 5) |
12 | DIPSW_2 | 11 | CLKHDR_CTRL14 | W26 | CM-PLL DIP Switch (position 6) |
14 | PLL_STATUS | 13 | CLKHDR_CTRL15 | V29 | AD9511 status signal (level shifted to 2.5v) |
18 | RFCLKBUF_OUT0_P | 17 | RFCLKBUF_OUT0_P | Output from WARP v3 RF Reference Clock buffer (AD9512 CLKOUT0+) | |
20 | RFCLKBUF_OUT0_N | 19 | RFCLKBUF_OUT0_N | Output from WARP v3 RF Reference Clock buffer (AD9512 CLKOUT0-) | |
24 | SAMPCLKBUF_CLK2IN_P | 23 | SAMPCLKBUF_CLK2IN_P | Input to WARP v3 Sampling Clock Buffer (AD9512 CLKIN2+) | |
26 | SAMPCLKBUF_CLK2IN_N | 25 | SAMPCLKBUF_CLK2IN_N | Input to WARP v3 Sampling Clock Buffer (AD9512 CLKIN2-) | |
30 | No Connection | 29 | SAMPCLKBUF_OUT1_P | Output from WARP v3 Sampling Clock Buffer (AD9512 OUT1+) | |
32 | No Connection | 31 | SAMPCLKBUF_OUT1_N | Output from WARP v3 Sampling Clock Buffer (AD9512 OUT1-) | |
36 | RFCLKBUF_CLK2IN_P | 35 | RFCLKBUF_CLK2IN_P | Input to WARP v3 RF Reference Clock Buffer (AD9512 CLKIN2+) | |
38 | RFCLKBUF_CLK2IN_N | 37 | RFCLKBUF_CLK2IN_N | Input to WARP v3 RF Reference Clock Buffer (AD9512 CLKIN2-) | |
5 | EXT_HDR_IN_D3 | 6 | CLKHDR_CTRL0 | V34 | Board-to-board Out Header IO[3] |
7 | EXT_HDR_IN_D2 | 8 | CLKHDR_CTRL1 | V33 | Board-to-board Out Header IO[2] |
9 | EXT_HDR_IN_D1 | 10 | CLKHDR_CTRL2 | V27 | Board-to-board Out Header IO[1] |
11 | EXT_HDR_IN_D0 | 12 | CLKHDR_CTRL3 | V28 | Board-to-board Out Header IO[0] |
15 | EXT_HDR_OUT_D0 | 16 | CLKHDR_CTRL4 | V32 | Board-to-board In Header IO[3] |
17 | EXT_HDR_OUT_D1 | 18 | CLKHDR_CTRL5 | W34 | Board-to-board In Header IO[2] |
19 | EXT_HDR_OUT_D2 | 20 | CLKHDR_CTRL6 | W30 | Board-to-board In Header IO[1] |
21 | EXT_HDR_OUT_D3 | 22 | CLKHDR_CTRL7 | W29 | Board-to-board In Header IO[0] |
25 | PLL_SCLK | 26 | CLKHDR_CTRL8 | Y34 | AD9511 SPI Interface Clock |
27 | PLL_SDO | 28 | CLKHDR_CTRL9 | Y33 | AD9511 SPI Interface Serial Data Out |
29 | PLL_SDIO | 30 | CLKHDR_CTRL10 | Y31 | AD9511 SPI Interface Serial Data I/O |
31 | PLL_CSn | 32 | CLKHDR_CTRL11 | Y32 | AD9511 SPI Interface Chip Select |
35 | REFCLK_BUF_OUTB1_N | 36 | CLKHDR_FPGA_CC_P | AD24 | Output from CM-PLL Reference Clock Buffer, connects to FPGA clock-capable pins (LVDS+) |
37 | REFCLK_BUF_OUTB1_P | 38 | CLKHDR_FPGA_CC_N | AE24 | Output from CM-PLL Reference Clock Buffer, connects to FPGA clock-capable pins (LVDS-) |
FPGA I/O
The WARP v3 clock module header has 16 pins connected directly to FPGA I/O. The CM-PLL uses all 16 pins, as listed in the table above.
Eight FPGA I/O are tied directly to the board-to-board headers. While these headers are labeled "In" and "Out" (indicating the role of the reference clock pin in each header), these 8 FPGA I/O can be used as any mix of inputs and outputs.
Two additional FPGA I/O are connected to the CM-PLL reference clock buffer. This connection allows the FPGA design to monitor the status of the PLL reference clock, independent of the PLL status. The w3_clock_controller core uses this connection to delay configuration of the PLL until a valid reference clock is observed. This simplifies the boot process for nodes connected in a daisy chain configuration. The reference clock buffer output uses LVDS signaling. The FPGA pins must implement LVDS termination to receive this clock signal. Use the IOSTANDARD = LVDS_25 and DIFF_TERM = TRUE constraints to enable LVDS termination in the FPGA IOBs.
WARP v3 Clock Buffer I/O
The CM-PLL circuits connect to the WARP v3 clock buffers. Specifically:
- The WARP v3 RF Reference Clock buffer output can be selected as a PLL reference clock on the CM-PLL module
- The WARP v3 RF Reference Clock and Sampling Clock buffers can be driven by the CM-PLL VCXO
The first connection allows a WARP v3 node equipped with a CM-PLL module to use its on-board TCXO as the frequency reference for the PLL, and to forward the reference to other CM-PLL via the board-to-board headers.
The second connection allows the CM-PLL to drive all the clock signals on the host WARP v3 board, enabling full synchronization of the sampling and RF reference clocks across multiple WARP v3 nodes.
The AD9511 PLL on the CM-PLL and the two AD9512 buffers on WARP v3 must be configured jointly to realize these configurations. Refer to the w3_clock_controller documentation for details on the standard configurations we use in the reference designs.