wiki:OFDMReferenceDesign/Changelog/Old

WARP OFDM Reference Design Revision History (Old Releases)

See the Changelog for the latest release


OFDM Reference Design v15.0 (2010-Aug-11)

The code and models for this design correspond to svn rev 1580 for the FPGA v1 design and svn rev 1585 for the FPGA v2 design.

Note: The PHY is functionally identical for FPGA v1 and v2. The v2 design uses HDL for 10 multipliers (in the Tx scaling and Rx coarse CFO correction blocks) instead of DSP48's. The V2Pro version of the PHY uses too many multipliers for the V4FX100 FPGA, but the V4 FPGA has more than enough logic to realize the extra multiplications in fabric.

Download the full XPS projects:

Both projects were built using the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386).

Hardware Changes

  • Rebuilt the Tx pilot insertion logic, to interleave pilots in time and space for Alamouti mode.
  • Rebuilt the Rx phase estimation and tracking systems to improve phase error and CFO performance.
  • Rebuilt the Rx correlator to improve packet detection performance, especially in Alamouti mode with two Tx antennas
  • Fixed random payload generator (it previously results in invalid checksums)
  • Added random payload capture logic, to write random payloads to a packet buffer for offloading via Ethernet for BER processing
  • Built a real CRC-16 calculator for the header checksums (reduces chances of checksum collisions)
  • Fixed bug in AGC core, which (very rarely) resulted in bogus DC offset correction values being applied for many packets in a row
  • Upgraded to clock_board_config_v1_05_a, adding support for run-time selection of local or off board clock sources.

Software Changes

  • Added support for the WARPnet Measurement Framework, including a new top-level application (WARPNET_EXAMPLE).
  • Updated warpphy/warpmac to reflect changes to registers in the PHY.

Using the Design

  • Same as v14.0 (see below).

OFDM Reference Design v14.1 (2010-Jan-08)

The code and models for this design correspond to svn rev 1400.
This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).

Download the full XPS project:

Hardware Changes

  • Updated the version of the Radio Bridge and Radio Controller cores to v1.22.a
  • Added the MGT Protector core to the Virtex-4 design to make sure the MGT tiles are always powered on. This is a requirement of the Virtex-4 (see 'Designing with MGTs' in Virtex-4 User Guide).

Software Changes

  • No software changes

Using the Design

  • Same as v14.0. See below.

OFDM Reference Design v14.0 (2009-Nov-15)

The code and models for this design correspond to svn rev 1400.
This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP3, EDK 10.1.03, Sysgen 10.1.3.1386).

Download the full XPS project:


FPGA Board Version Notes
The OFDM Reference Design uses very similar hardware designs for the two versions of the WARP FPGA Board (v1 and v2). The primary difference is the use of a soft Ethernet MAC in the Virtex-II Pro FPGA and hard TEMAC in the Virtex-4. The custom WARP peripherals (OFDM transceiver, AGC, timer, radio controller, etc.) are identical in both projects.

The software projects are also very similar across boards. The same source files are used for both versions. A few #ifdef statements are used in WARPMAC to include/exclude board-specific code at compile time. The primary difference is support for user I/O. The project for the FPGA Board v1 uses an xps_gpio core as an interface to the LEDs, hex displays, buttons and switches. The FPGA Board v2 project uses the custom warp_v4_userio core and driver for the user I/O. WARPMAC provides a single API for user I/O, so MAC-level code can be fully portable between FPGA Board versions.

Hardware Changes

  • Fixed phase tracking bug in the PHY; the bug caused packet errors when imperfect phase estimates were used mid-packet
  • Switched to TEMAC + LL_FIFO for the Ethernet interface (replacing ethernet_lite). This hardware design works on both FPGA Board v1 and v2, using a soft TEMAC for v1 and hard TEMAC for v2. The TEMAC and LL_FIFO together provide storage for 4 received packets, which improves the overall performance in systems where many packets may be received at once (like TCP).

Software Changes

  • Updated WARPMAC to use new Ethernet hardware
  • Updated WARPMAC with new user I/O code for FPGA Board v2. One code file works for both versions, using just a few !#ifdef to compile the correct code.

Using the Design

  • The included download-csmamac.bit file implements CSMAMAC; download-nomac.bit implements NOMAC. Both are ready to download to WARP SISO or MIMO Kits.
  • The included download-csmamac.ace or download-nomac.ace can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface.
  • The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default:
    • P/p : Increase/decrease the packet detection energy threshold by 100
    • D/d : Increase/decrease the packet detection required minimum energy duration by 1
    • C/c : Increase/decrease the carrier sensing energy threshold by 100
    • F/f : Increase/decrease the 2.4GHz center frequency by 1 channel
    • S/s : Use SISO via the radio in slot 3/2
    • A : Use Alamouti 2x1 (2 transmit antennas, selection diversity between 2 receive antennas)
    • 1/2/4/6 : Use BPSK/QPSK/16-QAM/64-QAM for the full-rate modulation scheme for all transmitted payloads
    • You can add other commands to tweak your own parameters in uartRecv_callback function
  • The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.
  • The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets.

OFDM Reference Design v13.1 (2009-Oct-1)

The code and models for this design correspond to svn rev 1330.
This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).

Download the full XPS project:

Using the Design

  • Same as version 13.0 (see below)
  • Two bitstreams are included, one for each software project: download-nomac.bit and download-csmamac.bit

Software Changes

  • Added NOMAC software project with code updated for v13 PHY/WARPMAC
  • Fixed XPS makefile project settings (thanks to HT for finding this)

OFDM Reference Design v13.0 (2009-Sep-26)

The code and models for this design correspond to svn rev 1326.
This project requires the latest versions of the 10.1 release of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).

Download the full XPS project:

Using the Design

  • The <project>/implementation/download.bit implements CSMAMAC and ready to download to WARP SISO or MIMO kits.
  • The <project>/system.ace file can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface.
  • The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default:
    • P/p : Increase/decrease the packet detection energy threshold by 100
    • D/d : Increase/decrease the packet detection required minimum energy duration by 1
    • C/c : Increase/decrease the carrier sensing energy threshold by 100
    • F/f : Increase/decrease the 2.4GHz center frequency by 1 channel
    • S/s : Use SISO via the radio in slot 3/2
    • A : Use Alamouti 2x1 (2 transmit antennas, selection diversity between 2 receive antennas)
    • 1/2/4/6 : Use BPSK/QPSK/16-QAM/64-QAM for the full-rate modulation scheme for all transmitted payloads
    • You can add other commands to tweak your own parameters in uartRecv_callback function
  • The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.
  • The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the left displays shows the sequence number of received packets.


Please use this forum thread to discuss results or questions about this reference design.

Hardware Changes

  • OFDM PHY Changes:
    • Added support for 2x1 Alamouti mode
    • Added new Auto Response subsystem to the PHY (DATA-ACK turnaround now just 17µs!)
    • Moved pilot tone phase estimator before equalizer so phase correction can be applied earlier
    • Added logic to adjust RSSI value in read-back register to compensate for RF gain choice
    • Shortened coarse CFO estimation window to 64 samples, to avoid corruption when the channel delay spread is non-zero
    • Moved the Tx scaling after the interpolation filters, so filter outputs (not inputs) can be saturated before transmission
    • Fixed (very old) bug with 64-QAM packets of certain lengths being declared bad
    • Fixed (old) phase error tracking bug to better handle wrapping phase error values; can now track larger CFO in frequency domain
    • Added pseudo-random payload generator

Software Changes

  • WARPMAC/WARPPHY:
    • Defined new user callback for WARPnet management packets received over Ethernet
    • Updated phyHeader definition to use 16-bit MAC addresses and to include third address
    • New macros to help configure the PHY's auto response system
    • Updated with new PHY registers and options
    • Added mode to generate traffic locally ("dummy packet" mode), emulating a fully-backlogged data source
  • CSMAMAC:
    • Updated to use PHY's auto response to automatically transmit ACKs
    • Updated to use WARPMAC's new dataFromNetworkLayer and mgmtFromNetworkLayer callbacks
    • Added support for receiving control packets and sending statistics packets over Ethernet

OFDM Reference Design v12.1 (2009-Apr-15)

The code and models for this design correspond to svn rev 1182.
This project requires the latest versions of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).
Download the full XPS project: OFDM_ReferenceDesign_v12_1.zip (65 MB)

Hardware Changes

  • Updated warp_timer hardware to use time slots during carrier sensing mode. The slot size can be configured to any number of clock cycles (including 0, effectively disabling slots). The timer interval is defined by slotCount- the number of time slots which pass before expiration. A slot will only decrement if the medium is completely idle during the slot. This behavior mimics the backoff mechanism in 802.11.
  • New warp_timer also includes 8 timers. The CSMA design uses 3 (backoff, timeout, user I/O). The remaining 5 are free for user applications. The slot count and slot length is configured per-timer.

Software Changes

  • Updated WARPPHY and WARPMAC for compatibility with new timer's registers.

OFDM Reference Design v12.0 (2009-Apr-9)

The code and models for this design correspond to svn rev 1171.
This project requires the latest versions of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).
Download the full XPS project: OFDM_ReferenceDesign_v12_0.zip (65 MB)

Hardware Changes

  • Packet detector updates
    • Integrated the RSSI-based packet detector core into the OFDM transceiver.
    • Removed the I/Q-based packet detector that was previously present. This is now only used in simulation.
    • The integrated detector's registers were rearranged (relative to the older separate detector core)
    • Added a minimum duration requirement to the packet detector. This block requires the average RSSI exceed the programmed energy threshold for a minimum number of cycles before the packet detecting output is asserted. The required minimum duration is programmable via a register.
    • Added logic to de-assert the IDLE for DIFS output whenever the transceiver is actively transmitting or receiving a packet. When either Tx or Rx is active, the medium is known to be busy, so the IDLE signal can safely be forced low, independent of RSSI readings.
  • Interrupt changes
    • Removed all interrupts in the hardware design
    • The transceiver now asserts register bits for reception events (good/bad header, good/bad packet); the MAC polls this register.
    • The user I/O and UART interrupts were replaced by polling the GPIO and UARTLITE registers.
    • The OFDM timer interrupts were replaced by polling the status of each timer in the core.
  • Upgraded EEPROM controller core HDL with better clocking design. Instead of generating a slow clock, the core generates a slow clock enable and uses the fast clock for all synchronous elements. This fixes the long-standing, intermittent timing error.
  • Fixed the PHY's handling of packet errors when all received bytes are zero. Previously this caused an erroneous good packet interrupt; now it correctly asserts the bad header and bad packet status bits.
  • Added a programmable saturating scale factor after the IFFT in the transmitter. This can increase the average transmission power at the cost of increased clipping. This scale factor has been defaulted to a value that jointly maximizes transmission power while minimizing transmitted EVM.

Software Changes

  • Updated WARPPHY and WARPMAC with register map for integrated transceiver and packet detector.
  • Updated EEPROM driver to match new hardware.
  • Replaced warpmac_pollEthernet with the more general warpmac_pollPeripherals
    • This function polls the timer, the PHY, and the Ethernet
    • One of the four timers in the warp_timer core is dedicated to the polling of the UART and User I/O buttons
  • Fixed bug in the function for setting random backoff timers found by forum user domenique (See post here). Previously the minimum contention window was [0,7]. This is now [0,15] like 802.11
  • Lowered packet detection threshold from 9000 to 6000. This should improve low SNR detection
  • Raised CSMA threshold from 6000 to 8192. This is more in line with 802.11 and should make nodes more aggressive in the presence of non-decodable interference

Using the Design

  • The <project>/implementation/download.bit is ready to download to WARP SISO or MIMO kits.
  • The <project>/system.ace file can be copied directly to a CompactFlash card (without using iMPACT) to program kits via the SystemACE CF interface.
  • The CSMAMAC code uses the UART to control various parameters at run time. Use a terminal emulator set to 57600bps. The following commands are implemented by default:
    • P/p : Increase/decrease the packet detection energy threshold by 100
    • D/d : Increase/decrease the packet detection required minimum energy duration by 1
    • C/c : Increase/decrease the carrier sensing energy threshold by 100
    • F/f : Increase/decrease the 2.4GHz center frequency by 1 channel
    • A/a : Use the radio in slot 3/2 for the active antenna in the SISO link
    • 1/2/4/6 : Use BPSK/QPSK/16-QAM/64-QAM for the full-rate modulation scheme for all transmitted payloads
    • You can add other commands to tweak your own parameters in the same UART callback
  • The four user LEDs are programmed by default to toggle based on packet receptions. The top two LEDs will toggle for each good packet received. The bottom two LEDs will toggle for each bad header or bad payload received.
  • The right seven-segment display is programmed to show the node's ID on boot (set by the DIP switch); the right displays shows the re-transmit count of each received packet.
  • The new interrupt-free design requires some minor modifications to user code from reference design v11.2
    • Call warpphy_pollPeripherals() in the main while(1) loop (instead of warpphy_pollEthernet()).
    • User code should still register callbacks for the various events (PHY good/bad Rx, timers, UART, user I/O); WARPMAC will execute these callbacks same as before (even though it's driven by polling instead of interrupts).


Please use this forum thread to discuss results or questions about this reference design.


OFDM Reference Design v11.2 (2008-Dec-1)

The code and models for this design correspond to svn rev 1128.
This project requires the latest versions of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).
Download the full XPS project: OFDM_ReferenceDesign_v11_2.zip

Hardware Changes

  • None; hardware is identical to v11.1

Software Changes

  • Updated radio controller driver to fix SetTxTiming function; the TxStart parameter was being ignored in v11 and v11.1 (due to hardware changes not correctly reflected in the corresponding driver calls)

OFDM Reference Design v11.1 (2008-Oct-18)

The code and models for this design correspond to svn rev 1111.
This project requires the latest versions of the Xilinx tools (ISE 10.1.03 + IP2, EDK 10.1.03, Sysgen 10.1.3.1386).
Download the full XPS project: OFDM_ReferenceDesign_v11_1.zip

Hardware Changes

  • Fixed a bug in the PHY that broke MIMO mode in refdes v11, related to the faster FFT in the receiver (thanks to the Drexel guys for finding it)

Software Changes

  • Updated CSMAMAC with better "routing" table (used to map node IDs to MAC addresses)
  • Updated warpphy's MIMO/SISO mode switching code to include RxScaling updates
  • ifdef'd in/out code to support future PHY with convolutional code support (v11.1 is uncoded - v12 will be first coded release)

OFDM Reference Design v11 (2008-Sep-2)

The code and models for this design correspond to svn rev 1064.
This project requires the latest versions of the Xilinx tools (ISE 10.1.02 + IP2, EDK 10.1.02, Sysgen 10.1.2.1250).
Download the full XPS project: OFDM_ReferenceDesign_v11.zip

Hardware Changes

  • Updated clock config core to latest version (fixes bad default values for en/disabled outputs)
  • Replaced ofdm_timer with new warp_timer peripheral (now includes four independent timers)
  • Reworked PHY to clock Rx FFT at system clock (40MHz).
    • This reduces the Rx latency by ~4µsec; DATA-ACK turnaround now 19.8µsec.
    • This also helps CFO, allowing the pilot tones to apply phase corrections one OFDM symbol earlier.
  • Redesigned pilot tone phase averaging to reduce intra-symbol variance.
  • Re-added shared memories for flexible Tx/Rx modulation (these were removed in v10 due to Sysgen 10.1.00 limitations).
  • Added User I/O board controller
  • Added interrupt for UART
  • Connected reset for secondary PLB46 (fixing bug found by patel_gaurav90)

Software Changes

  • New RTS/CTS implementation by Keith Wilhelm (undergrad intern in the CMC Lab)
  • Updated WARPMAC/WARPPHY with support for PHY changes
    • Updated timer wrapper functions for new warp_timer hardware
    • Updated modulation control function for new buffer structure
    • New UART ISR and user callback registration functions
  • New debug "MAC" top-level code to control/observe/debug PHY in hardware
  • Added basic Rx statistics display via the User I/O board LCD screen
  • Moved interactive debug menu to UART interrupt callback (instead of in main while(1) loop)
  • Updated AGC thresholds to better values (based on empirical tests)
  • Fixed support for MIMO mode in WARPMAC/WARPPHY (now correctly calculates PHY parameters in either SISO or MIMO mode)

OFDM Reference Design v10 (2008-Jul-17)

  • Known issue: see this forum post for details; this will be fixed in ref design v11
  • Download the XPS project: OFDM_ReferenceDesign_v10.zip
  • Built using cores and code as of repository revision 1010
  • This design requires version 10.1.02 of the Xilinx tools
  • Data-ACK turnaround time is now 23µs (as measured by the fall of data Tx to rise of ACK Tx)

Hardware Changes

  • Xilinx deprecated the OPB and PLB34 busses. PLB46 is the new (and only) bus standard used in this design
  • The System Generator cores (OFDM transceiver, timer, packet detector & AGC) were created using Sysgen's new PLB46 export flow; sysgen2opb is no longer required
  • Xilinx did not port the plb_ethernet EMAC forward to PLB46. This design uses the xps_ethernetlite EMAC instead, customized to enable promiscuous mode (i.e. no receive address filtering)
  • The xps_centraldma pcore is used to handle DMA (since the EMAC no longer provides its own DMA)
  • The OFDM transceiver has a new interrupt output indicating the reception of a bad header
  • Fixed a few logic bugs in the transceiver's handling of multiple interrupts
  • Merged all user I/O into single GPIO core (LEDs, hex displays, push buttons & DIP switch); a header file helps with the required bit masking/shifting. The XBD files have been updated to use the same user I/O scheme.

Software Changes

  • Ethernet is now operated exclusively in a polling mode for increased performance
  • WARPMAC/WARPPHY re-architected and cleaned; the code flows for transmitting and receiving packets are now consistent across various packet types
  • A layer of register access macros was added between WARPPHY and the OFDM cores; these macros adapt the old sysgen2opb register access code to the new Sysgen PLB46 export code. These macros will retired in a future revision.

OFDM Reference Design v09 (2008-Jun-11)

  • Download the XPS project: OFDM_ReferenceDesign_v09.zip
  • Built using cores and code as of repository revision 906
  • This version assumes a different location for TxDCO calibration information in the EEPROM of the radios. Please re-calibrate before running (instructions are here)
  • This will be the last reference design that will use the version 9 Xilinx tools. Reference Design v10 will use the version 10 Xilinx tools.
  • Updated warpmac/warpphy & csmamac
    • Header interrupts are used to pipeline receive processions (i.e. an ACK is constructed and loaded into a PHY before the packet is even completely received)
    • Fall of Tx data to rise of Tx ACK turn-around time reduced from 80 microseconds to 30 microseconds
    • By default, left and right push buttons use left and right radios respectively (only for MIMO WARP kits)
    • Numerous tweaks to MAC timing parameters

OFDM Reference Design v08 (2008-Feb-08)

  • Download the XPS project: OFDM_ReferenceDesign_v08.zip
  • Built using cores and code as of repository revision 834
  • Updated OFDM PHY
    • Added support for header-only packets (like ACKs); numFullRateSymbols can be zero
    • Last two bytes of header are now a 16-bit CRC of just the header
    • Added new interrupt output for good header; asserts for non-header-only packets when header CRC passes
    • Added TxDone interrupt output; asserts when a packet transmission finishes
    • Fixed bugs in dynamic modulation mask usage
  • Updated warpmac/warpphy & csmamac
    • Changes to support new PHY features
    • Added TxDone & GoodHeader interrupt handlers; unused in this version
    • Added lots of comments to the source code to better explain various MAC/PHY interactions
Last modified 10 years ago Last modified on Apr 26, 2011, 2:07:17 PM