WARP v3 AD Controller (w3_ad_controller)

This core implements an SPI master for reading/writing registers in the AD9963 analog converters on the WARP v3 board.

The w3_ad_controller core is packaged as a pcore which can instantiated in an XPS project. The design has been tested in hardware using Xilinx ISE 13.4.

Hardware

The w3_ad_controller HDL implements parallel SPI interfaces, one per RF interface. There are four ports per RF interface (3 SPI, 1 reset) which must be connected to the corresponding FPGA pins. Refer to the WARP v3 reference projects for examples of known-good hardware configurations.

The MHS snippet below shows the w3_ad_controller instantiation used in the WARP v3 reference projects. The memory address is intentionally invalid; you must run "Generate Addresses" after adding the core.

#Top level ports
...
# AD9963 ADC/DAC control pins (RFA & RFB)
 PORT RFA_AD_spi_cs_n_pin = RFA_AD_spi_cs_n, DIR = O
 PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
 PORT RFA_AD_spi_sclk_pin = RFA_AD_spi_sclk, DIR = O
 PORT RFA_AD_reset_n_pin = RFA_AD_reset_n, DIR = O
 PORT RFB_AD_spi_cs_n_pin = RFB_AD_spi_cs_n, DIR = O
 PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
 PORT RFB_AD_spi_sclk_pin = RFB_AD_spi_sclk, DIR = O
 PORT RFB_AD_reset_n_pin = RFB_AD_reset_n, DIR = O
...
BEGIN w3_ad_controller
 PARAMETER INSTANCE = w3_ad_controller_0
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0xFFFFFFFF
 PARAMETER C_HIGHADDR = 0x00000000
 BUS_INTERFACE SPLB = plb_primary
 PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
 PORT RFB_AD_reset_n = RFB_AD_reset_n
 PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
 PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
 PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
 PORT RFA_AD_reset_n = RFA_AD_reset_n
 PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
 PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
END
...

Driver

The w3_ad_controller pcore includes a C driver to facilitate control of the AD9963s from user code. Refer to the w3_ad_controller driver documentation for more details.

All driver functions require the base memory address of the w3_ad_controller pcore. This address is set in your XPS project. The EDK tools copy this address into a macro in the xparameters.h file when you generate a BSP. The auto-generated macro should be named XPAR_W3_AD_CONTROLLER_0_BASEADDR (assuming your pcore instance is named w3_ad_controller_0, as in the example above).

//Define our own macro, in case EDK changes its naming scheme in the future
// Assumes pcore instance is named w3_ad_controller_0; confirm in xparameters.h
#define AD_BASEADDR XPAR_W3_AD_CONTROLLER_0_BASEADDR

Source

The full hardware and software source code is available in the repository: PlatformSupport/CustomPeripherals/pcores/w3_ad_controller_v3_00_b. The VHDL, Verilog and C source code are made available under the WARP license.