1 | ################################################################### |
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2 | # Copyright (c) 2013 Mango Communications |
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3 | # All Rights Reserved |
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4 | # This code is covered by the WARP license |
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5 | # See http://warpproject.org/license/ for details |
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6 | ################################################################### |
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7 | |
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8 | BEGIN uart_mux |
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9 | |
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10 | ## Peripheral Options |
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11 | OPTION IPTYPE = PERIPHERAL |
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12 | OPTION IMP_NETLIST = TRUE |
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13 | OPTION HDL = VERILOG |
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14 | OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT) |
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15 | OPTION USAGE_LEVEL = BASE_USER |
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16 | OPTION DESC = Mango UART Mux |
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17 | OPTION IP_GROUP = USER |
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18 | OPTION RUN_NGCBUILD = FALSE |
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19 | OPTION STYLE = HDL |
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20 | |
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21 | IO_INTERFACE IO_IF = ext_uart_ports, IO_TYPE = MANGO_UARTMUX_V1 |
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22 | IO_INTERFACE IO_IF = user_ports, IO_TYPE = MANGO_UARTMUX_V1 |
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23 | |
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24 | PARAMETER C_FAMILY = virtex6, DT = STRING |
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25 | |
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26 | PARAMETER MIRROR_UART_RX = 0, DT = INTEGER, RANGE = (0:1), DESC = "Copy the UART input line to both UARTs; if 0 only the selected UART will receive data", PERMIT=BASE_USER |
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27 | |
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28 | #Control input (0=select uart_0) |
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29 | PORT uart_sel = "", DIR = I, IO_IF = user_ports, IO_IS = select, ASSIGNMENT = REQUIRE |
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30 | |
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31 | #Two UART Tx inputs (uartlite -> mux) |
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32 | PORT uart_0_tx = "", DIR = I, IO_IF = user_ports, IO_IS = uart_0_tx |
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33 | PORT uart_1_tx = "", DIR = I, IO_IF = user_ports, IO_IS = uart_1_tx |
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34 | |
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35 | #Two UART Rx outputs (mux -> uartlite) |
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36 | PORT uart_0_rx = "", DIR = O, IO_IF = user_ports, IO_IS = uart_0_rx |
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37 | PORT uart_1_rx = "", DIR = O, IO_IF = user_ports, IO_IS = uart_1_rx |
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38 | |
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39 | #Top-level UART connections |
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40 | # Tx = FPGA -> UART device |
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41 | # Rx = UART device -> FPGA |
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42 | PORT uart_tx = "", DIR = O, IO_IF = ext_uart_ports, IO_IS = uart_tx, ASSIGNMENT = REQUIRE |
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43 | PORT uart_rx = "", DIR = I, IO_IF = ext_uart_ports, IO_IS = uart_rx, ASSIGNMENT = REQUIRE |
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44 | |
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45 | END |
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