wiki:802.11/PacketFlow

Version 4 (modified by murphpo, 8 years ago) (diff)

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802.11 Reference Design: Packet Flow

As packets move through the 802.11 reference design, the packet contents must be accessible by CPU High, CPU Low and the PHY cores. The design achieves this using the interconnects illustrated in the figure blow.

Each MicroBlaze has access to two AXI interconnects. For both CPUs the MicroBlaze DP port (non-cached peripheral memory access port) is connected to an AXI4 Lite interconnect. The peripheral cores connected to each AXI4 Lite interconnect are accessible by only one CPU. The cores are divided between CPUs based on which part of the MAC needs to access them. For example the radio_controller, w3_ad_controller and PHY configuration registers are all attached to the interconnect for CPU Low. Similarly the Ethernet cores are attached to the peripheral bus for CPU High. The mailbox and mutex ports for each CPU are also attached to their corresponding peripheral busses.

The MicroBlaze DC (cached memory access port) for both CPUs are attached to a shared AXI4 interconnect. The data cache is disabled in the Reference Design; all memory access via the DC ports access a slave memory device via the AXI4 interconnect. Both CPU DC ports are masters on this interconnect. The primary slave devices on this interconnect are the block RAMs used to implement the packet buffers (discussed below). Both CPUs can read and write any location in both memories. The AXI4 interconnect is a 64-bit crossbar clocked at 160MHz, which provides sufficient throughput to avoid contention between the CPUs.

Packet Buffers

The 802.11 Reference Design uses two dual-port 64KB RAMs as Tx and Rx packet buffers. One port of each RAM is attached to a BRAM interface controller (axi_bram_ctrl), which maps the RAM onto the address space of the two CPUs. The other port of each RAM is attached directly to the corresponding PHY core. These direct PHY connections do not traverse an AXI interconnect. Instead both PHY cores (Tx and Rx) implement native 64-bit BRAM interfaces in logic.

The PHY cores divide each 64KB BRAM into 16 4KB buffers. The PHY numbers these buffers [0:15]; the low-level MAC code provides the packet buffer index to the PHY for each Tx and Rx event.

Packet Buffer Contents

Each packet buffer stores more than just the raw Tx/Rx bytes for the PHY. The MAC uses each buffer to store other metadata. The contents of each packet buffer are illustrated below.

The MAC code utilizes the first section of each packet buffer for metadata about the packet contained in that buffer. This metadata is stored in the tx_frame_info and rx_frame_info structs, defined in wlan_lib.h.

The second section is the PHY header. For Tx packets the MAC must populate this section with a valid SIGNAL field. When a new transmission is initiated the Tx PHY will read these bytes first to determine the modulation/coding rates and payload length. The Tx PHY will terminate immediately if the SIGNAL bytes are invalid. For Rx packets the PHY will write the raw SIGNAL field bytes to the PHY header area. This is useful for debugging; for normal Rx processing the MAC will be notified of the Rx length and rate via registers in the DCF MAC core.

The final section of each packet buffer is the packet payload (a.k.a. the MPDU, for data frames, MMPDU for management frames). The Rx PHY does not interpret these bytes in any way. The MAC code must ensure this section of the packet buffer contains a valid MAC header and corresponding payload.

Checksums

The 802.11 standard requires Frame Check Sequence (FCS) be attached to all transmitted frames. The checksum is calculated using the standard CRC32 scheme and covers all bytes of the MAC payload. The 32-bit checksum is always transmitted as the last 4 bytes of the packet payload.

The Tx PHY automatically calculates and inserts the 32-bit checksum in the transmitted packet. The MAC code must include the FCS bytes in the length value in the SIGNAL field, but the MAC code does not need to calculate the actual checksum. The FCS values calculated by the Tx PHY are not written to the Tx packet buffer.

The Rx PHY automatically calculates the checksum of every received frame and provides an FCS_GOOD indication to the MAC hardware core immediately upon reception of the final byte of a packet. The received FCS bytes are written to the Rx packet buffer; these can be safely ignored by the MAC code.

Mutexes

A 32-entry mutex is used to avoid contention for Tx and Rx packet buffers between CPUs. One mutex entry corresponds to one packet buffer.

CPU High locks a Tx packet buffer while it prepares a packet for transmission. It unlocks the buffer when it notifies CPU Low (via the mailbox) that the new packet is ready for transmission. CPU Low locks the Tx buffer while it awaits the PHY transmission, unlocking the buffer when it notifies CPU High of completion.

CPU Low locks the Rx packet buffer into which the Rx PHY is writing received packets. When the PHY notifies the MAC a packet has been received without errors, CPU Low locks another Rx buffer and configures the Rx PHY to begin receiving new frames there. CPU Low unlocks the buffer containing the valid received frame and notifies CPU High. CPU High locks the packet buffer and processes the received packet. When its processing is finished, it unlocks the Rx packet buffer, allowing CPU Low to use it for a future reception.

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