wiki:HardwareUsersGuides/FMC-RF-2X245/RF

FMC-RF-2X245 User Guide: RF Interfaces

The FMC-RF-2X245 board integrates two identical RF interfaces. The basic structure of each interface is illustrated below.

On the FMC-RF-2X245 board these interfaces are labeled RF A and RF B. When used on a WARP v3 board, these interfaces will generally be referred to as RF C and RF D, to avoid conflicting with the WARP v3 on-board RF interfaces.

AD9963 ADC/DAC

The conversion between the analog I/Q and digital I/Q domains is handled by the Analog Devices AD9963 MxFE. The AD9963 integrates two 100MSps 12-bit ADCs, two 170MSps 12-bit DACs, interpolation and decimation filters and programmable analog gain and offset adjustments. Refer to the ADI AD9963 datasheet for full specifications.

The AD9963 is very flexible and includes a register bank to control various functions on the chip. The registers are accessed via a dedicated SPI interface. We have designed the w3_ad_controller core to access the AD9963 registers via the SPI interface when using this FMC module on a WARP v3 kit.

The digital I/Q ports on the AD9963 operate at double data rate, with I/Q interleaved. We have designed the w3_ad_bridge core to connect these DDR ports to separate internal I/Q busses in user designs. One instance of the w3_ad_bridge core implements the interface to both RF interfaces. WARP v3 designs with four antennas will use two instances of the w3_ad_bridge bridge.

Tx Data Path

The AD9963 integrates 3 stages of digital interpolation filters. These filters can be en/disabled at run time via SPI register writes. By cascading the filters the AD9963 can apply interpolation of 1x, 2x, 4x or 8x.

A single AD9963 Tx data path is illustrated below. Identical data paths are implemented for both DACs (I and Q).

Int Rate Enabled Filters
1 None
2 INT0
4 INT0, INT1
8 INT0, INT1, SRRC

The figures below show the effective frequency response of the Tx path for interpolation rates 2, 4, and 8. The frequency axis is normalized to the DAC sampling rate. Click each figure for the full-resolution. These figures come from pg. 38 of the AD9963 datasheet.

2x Interpolation 4x Interpolation 8x Interpolation

Refer to the AD9963 datasheet for the coefficients used in each interpolation filter.

Note that when the interpolation filters are enabled, the user-supplied Tx I/Q samples and the DAC sampling clock run at different frequencies. The user design must ensure the data clock (TXCLK) frequency, DAC clock frequency and interpolation filter settings are in agreement.

Rx Data Path

The AD9963 integrates a digital 2x decimation filter. This filter can be en/disabled at run time via an SPI register write. A single Rx data path is illustrated below. Identical data paths are implemented for both ADCs (I and Q).

The effective frequency response when the decimation filter is enabled is shown below. This figure comes from pg. 37 of the AD9963 datasheet. Refer to the datasheet for the actual coefficients used in the decimation filter.

2x Decimation

Note that when the decimation filter is enabled, the Rx I/Q samples and TRXCLK signal will run at a different rate than the ADC sampling clock. The user design must ensure the FPGA clock design and AD9963 filter/clock settings are in agreement.

Clocking

The clocking configuration of the AD9963 is flexible and, as a result, complicated. There are two main clock domains in the AD9963: data clocks, connected to the FPGA, and converter clocks, used by the ADC/DAC cores.

The converter clocks are illustrated below.

Notice that the DAC and ADC clocks are always derived from the AD9963 reference clock input, not the data clock inputs. The data clocks must be synchronous to the converter clocks, but by separating these domains preserves the low jitter of the original reference clock.

The DLL parameters (M/N), ADC clock divider and mux selects are all configured via SPI register writes. The correct settings depend on the desired sampling rate, the Tx and Rx data rates at the FPGA and the AD9963 rate-change filter settings.

The REF_CLK signal is generated by the sampling clock buffer on the FMC-RF-2X245 board. This signal is derived from the 80MHz TCXO and can be divided by the clock buffer before being driven to the AD9963s. Refer to the FMC-RF-2X245 Clocking page for more details.

Some examples of valid combinations of clock sources, clock frequencies and filter settings are listed below. Many other valid combinations are possible. Note that the w3_ad_bridge and w3_ad_controller do not enforce valid combinations, as these cores do not know what clocks are connected in hardware. The user design must ensure correct settings.

Example 1

  • Tx I/Q data rate = 40MHz (FPGA-generated TXCLK = 40MHz)
  • Interpolation: 1x (INT0, INT1, SRRC bypassed)
  • Rx I/Q data rate = 40MHz (AD9963 TRXCLK output = 40MHz)
  • Decimation: 1x (DEC bypassed)
  • REF_CLK = 40MHz (sampling clock buffer divider set to 2)
  • ADCDIV = 1
  • DAC_CLK = REF_CLK (40MSps)
  • ADC_CLK = REF_CLK (40MSps)

Example 2

  • Tx I/Q data rate = 40MHz (FPGA-generated TXCLK = 40MHz)
  • Interpolation: 4x (INT0, INT1 enabled; SRRC bypassed)
  • Rx I/Q data rate = 40MHz (AD9963 TRXCLK output = 40MHz)
  • Decimation: 2x (DEC enabled)
  • REF_CLK = 80MHz (sampling clock buffer divider set to 1)
  • DLL M/N = 2/1 (DLL_CLK = 2*REF_CLK = 160MHz)
  • ADCDIV = 1
  • DAC_CLK = DLL_CLK (160MSps)
  • ADC_CLK = REF_CLK (80MSps)

Example 3

  • Tx I/Q data rate = 80MHz (FPGA-generated TXCLK = 80MHz)
  • Interpolation: 2x (INT0 enabled; INT1, SRRC bypassed)
  • Rx I/Q data rate = 80MHz (AD9963 TRXCLK output = 80MHz)
  • Decimation: 1x (DEC bypassed)
  • REF_CLK = 80MHz (sampling clock buffer divider set to 1)
  • DLL M/N = 2/1 (DLL_CLK = 2*REF_CLK = 160MHz)
  • ADCDIV = 1
  • DAC_CLK = DLL_CLK (160MSps)
  • ADC_CLK = REF_CLK (80MSps)

Example 4

  • Tx I/Q data rate = 10MHz (FPGA-generated TXCLK = 10MHz)
  • Interpolation: 8x (INT0, INT1, SRCC enabled)
  • Rx I/Q data rate = 20MHz (AD9963 TRXCLK output = 20MHz)
  • Decimation: 2x (DEC bypassed)
  • REF_CLK = 80MHz (sampling clock buffer divider set to 1)
  • ADCDIV = 2
  • DAC_CLK = REF_CLK (80MSps)
  • ADC_CLK = REF_CLK (40MSps)

MAX2829 Transceiver

The FMC-RF-2X245 RF interfaces use the Maxim MAX2829 transceiver to translate between baseband and RF. The MAX2829 implements both 2.4 and 5GHz Tx/Rx paths. For full specifications refer to the MAX2829 datasheet.

The MAX2829 transceiver has a number of digital control lines and a dedicated SPI interface for internal register access. We have designed the radio_controller core to manage these control interfaces in user designs.

Each transceiver generates its own RF carrier signal, derived from a reference clock input. The reference clocks for both RF interfaces are driven by an AD9512 clock buffer (see for details). The MAX2829 requires either a 20MHz or 40MHz reference clock. The AD9512 must be configured to divide its 80MHz input to generate the desired reference frequency.

Power Amplifier

The FMC-RF-2X245 design currently uses the Anadigics AWL6951 dual-band power amplifier. Every board is tested to ensure >20dBm output power at both 2.4 and 5GHz. Refer to the AWL6951 datasheet for full specifications.

RF Port

Each RF interface is connected to a 50 ohm SMA jack. This connector is a standard polarity, standard thread SMA jack. The SMA jack should always be terminated into a 50 ohm load. The FMC-RF-2X245 kit includes SMA terminators for each RF interface. Users must supply their own RF cables or antennas to suit their application.

The maximum input power at the SMA connector should never exceed 0dBm, to avoid damage to the MAX2829 RF inputs.

The performance of the MAX2829 RF inputs are specified for input powers below approximately -10dBm. To connect two FMC-RF-2X245 kits via a coax cable, ensure there is at lest 40dB series attenuation.

Last modified 6 years ago Last modified on Jan 16, 2013, 3:48:27 AM