You are not logged in.
Hello all:
Just a quick question. Page FPGA Config states that "Positions 2-4 of the DIP switch select which configuraiton [sic] slot on the SD card should be used for configuration. For example, to select slot 2 on the SD card, set the DIP switch to: "
My problem with learning from ambiguous examples... What is the bit ordering of positions 2 to 4, from most to least significant bit? :)
Thanks in advance!
Last edited by David Garcia-Roger (2015-Nov-30 03:22:51)
Offline
I'm pretty sure the pins are mapped such that the slot selection value MSB is on the left (i.e. slot_val[2:0] = dip_sw_pos[2:4]). This is based on tracing the pin assignments from the schematics to the CPLD design constraints and HDL. I'm out of the office for a few days, so I can't actually test this to be certain.
Offline
Patrick is right, bit position 2 (towards the RAM) is the MSB.
Offline
Thank you for your quick reply! :)
Offline