wiki:802.11/MAC/Lower

Lower-level MAC Description

The lower level MAC interfaces directly to the PHY Tx and Rx cores and handles all wireless transmissions and receptions. Minimizing processing latency in the lower level MAC is critical in order to meet the 802.11 channel access timing requirements.

Minimal state is maintained at this level. Only the contention window and station retry counters are stored across packet transmission events. All other state (AP vs. STA, association state, etc.) is maintained by the upper layer MAC.

Processing in the lower level MAC is divided across two resources:

  • The C code in the CPU Low MicroBlaze core (wlan_mac_dcf.c)
  • The MAC support core in the FPGA fabric

The C code interfaces with the upper layer MAC via the inter-processor mailbox and accesses the Tx/Rx PHY via the MAC support core.

The MAC support core connects directly to the Tx/Rx PHY control and status signals. It also implements the timers and state machines required to meet the 802.11 channel access timing requirements. The core is controlled from the lower level MAC C code.

Last modified 3 years ago Last modified on Aug 10, 2015, 1:22:43 PM