WARP FPGA Board Clocking

On-board Oscillators

The FPGA board has two oscillator footprints for general clocks. By default, one 100MHz oscillator is mounted (component Y5) and one footprint is left empty (component Y6) for future customization. Both oscillator footprints are connected to global clock (GCLK) pins on the FPGA.

Off-board Clock Sources

The FPGA board has a header dedicated to off-board clocks. This header (component J29) is generally used by the WARP Clock Board.

SystemACE CF Clocking

The SystemACE CF controller requires a 33MHz clock which runs at all times. The FPGA requires a copy of this clock in order to use the SystemACE controller's microprocessor interface. A dedicated 33MHz oscillator (component Y4) is used on the FPGA board to supply this clock. The oscillator's output is split and driven to both the FPGA and the SystemACE CF controller.

MGT Clocking

Please see MGTs for details on clocking the FPGA's multi-gigabit transceivers.